Advance Information
MUPA64K16 “Alto” Priority Queue Scheduler
General Description
The MUPA64K16 Alto Priority Queue Scheduler is a
high-performance sorting engine designed to support
packet scheduling in high-speed switch or router
applications. Alto can support any scheduling
algorithm for which a priority queue is required, such
as Weighted Fair Queuing, Start-Time Fair Queuing
and Self-Clocked Fair Queuing.
Alto holds 65,536 entries, each of which consists of a
32-bit sorting key and a 16-bit associated data value.
These 65,536 entries may be distributed evenly
across one, two, four, eight or sixteen independent
priority queues, where the number of elements
occupied in each of these queues is indicated by a
size register. Thus, Alto can support up to 65,536
FIFO queues distributed across up to 16 physical
switch ports.
Alto has a simple synchronous 32-bit interface as
well as a separate bus for expanding the associated
data field using external SRAM.
Features
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Priority Queue with insert, extract and peek
operations
Packet processing time of 150 ns
65,536 priority queue entries
32-bit sorting key
16-bit associated data value
Supports up to 65,536 FIFO queues
Supports up to 16 physical switch ports
Wrap register per port handles counter roll-
over
UID Manager generates unique associated
data values
32-bit synchronous data interface
17-bit SRAM address bus
15 ns clock
1.8V core / 3.3V I/O
128-pin LQFP package (14 x 20 mm)
Industrial Temperature grade available
IEEE 1149.1 JTAG boundary scan logic
FIFO 1
Packet Input
FIFO 2
Packet Output
FIFO N
Packet
Classifier
Control ASIC
Packet Scheduler
MUSIC
Semiconductors
Alto
Figure 1: Packet Scheduling System Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase “MUSIC Semiconductors” are Registered Trademarks of MUSIC
Semiconductors. “MUSIC” is a trademark of MUSIC Semiconductors.
MUSIC Semiconductors Confidential
1
April 20, 2001 Rev 0.3 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
