MUPA64K16 Alto Priority Queue Scheduler
In both methods described, it is important to note that
Since the internal device requires 2200 clock cycles
(a duration of 33 ms) to initialize; no instructions
should be issued within this time period.
the logic levels present at each of the hardware
configuration pins are also latched into Alto as a
function of the reset operation (hardware or
software). These hardware configuration values are
guaranteed to be latched into Alto 100ms after the
deassertion of the RESET pin.
INSTRUCTION SEQUENCES
The basic operation of Alto is simple. For input
operations, data is written to registers and the
operation is started. For output operation, the
operation is started and the results are read from
registers when the operation is complete. Figure 4
shows the normal data flow through Alto.
The hardware configuration values latched into the
during the reset operation are dependent upon the
logic levels present at Alto pins, upon power-up. The
66MHz clock reference must be applied for reset to
take effect.
The way to perform each basic operation is shown
below. Operation completion can be determined
using the Status Register, using the status pins
(STR[4:0]) or by counting clock cycles.
Hardware Reset
The hardware reset operation requires that the reset
pin (/RST) be asserted for a minimum of three
continuous clock cycles during normal operation.
When the hardware reset operation occurs as the
part of power-up sequence; the PLL requires a lock
time of 100 ms based on external clock. Only after the
PLL has locked the frequency will the instructions be
recognized.
The Insert, Extract, Both, and Peek operations are
performed as shown in Tables 6, 7, 8, and 9. A UID
Get operation is performed as shown in Table 10,
and a UID Put operation is performed as shown in
Table 11.
Operations can be pipelined and interleaved; also,
priority queue operations and UID manager
operations can execute in parallel. When an
operation is started, the values of the appropriate
registers are loaded into the execution unit. The input
registers are available to hold new input values. If a
new operation is requested of an execution unit that
is busy, the new operation will begin as soon as the
previous operation is complete. The instruction FIFO
for each execution unit is one deep; issuing two or
more new instructions to an execution unit that is
busy will cause only one of the instructions to
execute.
The PLL in Alto requires 100ms to stabilize after reset
and no commands should be issued during this time.
Also, the UID manager requires an additional 2200
clock cycles to initialize after this 100ms interval.
The MDR, MKR, MR, SRs, UGR and WRs all are
reset to zero. The STR (Status Register) should
become 0001. After 2200 clock cycles to initialize the
UID system, the STR should become 0101.
Software Reset
The software reset operation can be accomplished by
writing into the Mode Register. This will cause a
software reset of the device, even if Alto has recently
completed a hardware reset. When more than one
priority queue is desired, the Mode Register must first
be set to the appropriate value. The software reset
takes approximately 100ms. Both the hardware reset
and software reset will reset Alto such that all
registers and state machines will be reset to default
values and the hardware configuration values will be
re-latched into Alto (similar to power-up/reset
operation). Driver code should wait 100ms following a
software reset before interfacing with the device.
Input Data
Register
Input Key
Register
Min Data
Register
Min Key
Register
Size Register
x16
Wrap
Register x16
Mode
Register
Status
Register
UID Put
Register
UID Get
Register x16
Priority Queue
UID Manager
Figure 4: Dataflow diagram
MUSIC Semiconductors Confidential
9
Rev 0.3 Draft
MUSIC [ MUSIC SEMICONDUCTORS ]
