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The /MF output indicates whether a match was found. The
JTAG interface is able to set /MF to HIGH-Z.
The TDI input is the Test Data input. Internally pulled up
with 25K minimum.
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The /TRST is the Test Reset pin. Internally pulled up with
25K minimum. Must be tied to /RESET or tied LOW
when not in use.
The TDO output is the Test Data output.
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These pins are the power supply connection to the MUAA
RCP. VCC must meet the voltage supply requirements in
the Operating Conditions section relative to the GND pins,
which are at 0 Volts (system reference potential), for
correct operation of the device. All the ground and power
pins must be connected to their respective planes with
adequate bulk and high frequency bypassing capacitors in
close proximity to the device.
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The /TCLK input is the Test Clock input. Must be tied at a
valid logic level when not in use.
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The TMS input is the Test Mode Select input. Internally
pulled up with 25K minimum.
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a search just returns RAM. Where the
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CAM/RAM partition does not lie on a port width
boundary the last word of the read may contain undefined
data in the most significant bits. The number of unload
cycles actually completed is optional.
In order to keep data alignment simple, the number of
words to be loaded and unloaded for each operation is kept
consistent for each CAM/RAM partition configuration and
the width of the port.
The DOUT register stores the results of operations from
the asynchronous processor port. Search results are
obtained by repeated reads of DOUT until all RAM data is
read. When performed from the processor port, READ
LQUEUE and READ AQUEUE return the first segment
of CAM data on the cycle that requests the operation;
additional CAM and RAM segments are obtained by
repeated reads of the DOUT register.
Tables 1 and 2 show the cycle sequence and CAM/RAM
bit mappings for 32- and 16-bit bus modes. The bus may
be selected for each port independently. Table 3 shows
whether CAM, RAM or both types of segments are used
on input or output cycles for each operation.
Loads always start right aligned from the least significant
word, CAM partition first, followed by RAM if necessary.
Most instructions do not require the entire 80 bits to be
loaded.
Loading is flow controlled on the synchronous DIN port
with the DINREADY signal, which is HIGH when data is
accepted by the DIN port. On the Processor port the
PROCREADY signal is HIGH when the current write
cycle may complete.
CAM data is required as an input for all operations except
READ LQUEUE and READ AQUEUE. The use of RAM
data is optional (i.e., it is not necessary to perform all
RAM cycles when inputting data). However, the user must
be aware that INSERT and LEARN operations will
over-write RAM data. Therefore, the application should
remain consistent in the number of RAM bits used for
these operations.
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On the synchronous port, operations are started on the
CLK cycle in which the requested Op-Code is written. On
the processor port operations are started when the chosen
operation register is written. The user should use the flow
control mechanisms to determine when results are avail-
able. On the synchronous port the /DOUTVALID signal is
asserted for one CLK cycle when new data is written to
the DOUT port. The processor port will assert its
PROCREADY signal on the CLK edge that data is avail-
able. Note that there is no internal flow control from the
sync DOUT port back to the sync DIN port. The DOUT
data is overwritten if it is not unloaded.
All CAM and RAM segment writes except the last use the
LOAD instruction. The last segment of data uses the
instruction for the desired operation.
Depending on the operation, unloads either start from the
right aligned, least significant word of CAM followed by
the right aligned, least significant word of RAM or just
from the right aligned, least significant word of RAM. For
instance, a QUEUE read returns CAM then RAM,
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