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Note: Signal names that start with a slash (“/”) are active LOW. All signals are 3.3 Volt CMOS level. All input
and bi-directional pins are 5-Volt tolerant, except for CLK. Never leave inputs floating except where
indicated. The CAM architecture draws large currents during search operations, mandating the use of good
layout and bypassing techniques. Refer to the Electrical Characteristics section for more information.
GND
DOUT1
DOUT2
DOUT3
DOUT4
VCC
DOUT5
DOUT6
DOUT7
VCC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
CHAINDN
CHAINUP
GND
CHAIN3
CHAIN2
CHAIN1
CHAIN0
GND
CHAINCS
GND
DOUT8
PROCD31
PROCD30
PROCD29
PROCD28
PROCD27
PROCD26
PROCD25
PROCD24
VCC
PROCD23
PROCD22
PROCD21
PROCD20
PROCD19
PROCD18
GND
PROCD17
PROCD16
PROCD15
PROCD14
PROCD13
PROCD12
VCC
DOUT9
DOUT10
DOUT11
VCC
DOUT12
DOUT13
DOUT14
DOUT15
GND
DOUT16
DOUT17
DOUT18
DOUT19
VCC
DOUT20
DOUT21
DOUT22
DOUT23
GND
DOUT24
DOUT25
DOUT26
DOUT27
VCC
DOUT28
DOUT29
DOUT30
DOUT31
GND
160-Pin
PQFP
149
150
151
50
49
48
47
46
45
44
43
42
41
152
153
154
155
156
157
158
159
160
PROCD11
PROCD10
PROCD9
PROCD8
PROCD7
PROCD6
GND
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DIN[31:0] are synchronous port data input pins. Data is
loaded into the MUAA RCP right aligned, least significant
word first.
OP[3:0] is a synchronous port operation to be performed on
the data applied to the DIN pins. OP is sampled by the rising
edge of CLK when /DINE is asserted. When loading the
CAM/RAM words to DIN, OP is set to LOAD except for the
last word. OP for the last word is set to the desired operation.
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DIN is sampled by the rising edge of CLK when /DINE is
asserted.
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MUSIC [ MUSIC SEMICONDUCTORS ]
