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Sync Port cycle3 starts at CLK8, which is the DA search
of the next frame.
The processor cycle data requested earlier, can now
become available at CLK21. PROCREADY is asserted
HIGH by the device to indicate that the cycle may be
completed. The first 32-bit word is available on the
PROCD bus and can be read by the processor. The two
remaining 32-bit words that complete the LQUEUE entry
are read by the subsequent processor cycles. These cycles
do not require access to the CAM core, hence the
PROCREADY signal is asserted immediately once the
cycle is initiated. The processor may use the LQUEUE
data to maintain a management database of MAC
addresses and associated port IDs.
AT CLK 10 the results of the cycle2 learn operation are
available. /MF was not asserted LOW; therefore the 48-bit
CAM partition data was not found during the compare.
The MUAA RCP automatically writes the 80-bit
CAM/RAM word into the next free location of the
memory array along with the most up to date time stamp
or entry life. The address index is available from the
DOUT bus to indicate where in the memory array the data
was placed. This can be used to implement further associ-
ated data in software or hardware. Furthermore, the INT
output is asserted to indicate that the “learned” word was
entered into the LQUEUE.
Back to back DA searches are shown from CLK25 onward.
This is to demonstrate how the synchronous port
handshaking works using the /DINREADY output. Sync
port cycle5 and cycle6 are completed normally but at
CLK29 /DINREADY goes LOW to indicate that the
MUAA RCP cannot accept the load operation of sync
cycle7. Therefore the host must hold the DIN, OP, and
DINE signals active until /DINREADY goes HIGH. At this
point the MUAA RCP will return /DINREADY to HIGH to
indicate that it has accepted the DIN and OP information.
Sync Port cycle4, which is the SA learn of the same frame
as Sync Port cycle3, is initiated at CLK10.
The processor can also be used to access the MUAA RCP
for general housekeeping duties. The LQUEUE contains
the contents of the virtual learned queue. A processor cycle
is started around CLK12 to read the LQUEUE register.
This cycle is unable to be completed because the CAM
core is busy servicing the synchronous port. PROCREADY
remains inactive to inform the processor of the delay. The
cycle is therefore extended and will complete when the
MUAA RCP asserts PROCREADY HIGH.
/MF is asserted LOW to indicate a match result on the
CAM partition compare. At this point DOUT will be used
to transfer the associated data and the address index of the
matching condition. The associated data is available first
(RAM partition) and would normally contain the port ID
in a typical switch. The RAM partition is configured as 32
bits wide and can therefore be transferred in one CLK
period. /DOUTE is asserted by the user to transfer the next
word of data on the next clock period. As the RAM takes
only one cycle, the address index is available after the
associated data.
The result of cycle4, which was a SA learn, is available at
CLK17. The learn instruction produced a match result.
There was no need to overwrite the CAM/RAM partitions,
but the MUAA RCP automatically updated the time stamp
or entry life of the matching entry. The address index of
the entry becomes available at the DOUT port.
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MUSIC [ MUSIC SEMICONDUCTORS ]
