Operational Characteristics
MU9C4320L ATMCAM
OPERATIONAL CHARACTERISTICS
loading a new instruction. After a Comparison cycle,
Write at Next Free Address cycle or Read/Write at
Highest-Priority match in a vertically cascaded system,
only the highest-priority device will enable its DQ31–0
lines and output the contents of its Status register. After a
Comparison cycle, in the event of a mismatch in the CAM,
the DQ31–0 lines of the lowest-priority device will be
enabled. After a random access Read or Write cycle, the
Status register of any selected device will be enabled.
Under these circumstances, it is up to the user to ensure
that only a single device is enabled through /CS1, /CS2, or
the Device Select register.
Processor Interface
The processor interface is through a 32-bit data bus
DQ31–0 and control signals comprising Chip Enable (/E),
two Chip Selects (/CS1, /CS2), Write Enable (/W), Output
Enable (/OE), Validity Bit Control (/VB), Address Valid
(/AV), and Address/Control inputs (AC11–0). When the
/AV line is LOW, the AC11–0 lines carry an address for
random access into the Memory array; when it is HIGH,
the AC11–0 lines convey control information.
Most of the functionality of the ATMCAM is accessed
through the control states on AC11–0 when /AV is HIGH.
The processor maps the control structure into memory
space and controls the ATMCAM through memory Read
and Write cycles. Using this memory mapping scheme, the
/AV line should be driven from logic that generates a
HIGH level within the mapped range of the control states,
and a LOW level outside it. Other control inputs /E, /W,
/CS1, and /CS2 are analogous to SRAM control inputs.
The instruction is persistent, so that all subsequent data
transactions will be executed according to the control state
held in the Instruction register. The results of a
Comparison cycle can be read back from the Status
register, and include PA3–0:AA11–0, /MF, /MM, /MV,
and /FF. The following sequence of events provides the
fastest operation of the ATMCAM in Software Control
mode:
The /VB line acts like an extra data bit during memory
Read and Write cycles and is used to read and write the
validity of any memory location.
/AV
1
Operation
Load ‘Compare DQ with CAM’ instruction
Comparand on DQ31–0
Read Status register
0
The ATMCAM is enabled either through hardware
through /CS1 or /CS2 being LOW, or it is enabled by the
value written to the Device Select register matching with
the Page Address field of the Configuration register. One
extra bit in the Device Select register enables the
comparison between the Page Address value and the
Device Select register. These Chip Select mechanisms
operate in parallel. If any one is active, the device is
enabled.
1
0
Next Comparand on DQ31–0
Read Status register, etc.
1
Note: It is up to the system designer to ensure that the correct
cycle type follows the loading of an instruction in Software
Control mode. If the instruction expects a Read cycle, and a
Write cycle is executed, or vice versa, the function of the
ATMCAM is undefined. Such an error may lead to data loss, but
will not damage the device physically.
The ATMCAM can be controlled directly through
software. The Software Control mode is selected through
settings in the Configuration register.
The ATMCAM supports VP Table lookup. This function
is selected through the Configuration register. By default
the VP Table lookup is disabled. When selected, the
function is implemented through a 4K x 1 table addressed
by the upper-order 12 bits of the Comparison Data bits
31–20. The lowest-priority device within a vertically
cascaded system holds the VP Table. The function is
disabled in all other devices through the setting in the
Configuration register. Because the VPI field is 12 bits, the
VP Table is entirely contained within the 4K depth of a
single ATMCAM. Note that when the VP Table is
disabled, the VP Table control states are still active. In
other words, even when disabled, the VP Table bits can be
read, set, and reset.
When the Software Control mode is selected, control
states are written to the Instruction register from DQ11–0
during a Write cycle with the /AV line held HIGH. If the
control state does not involve any data transaction on the
DQ31–0 lines, the instruction is executed during the same
cycle; the state of DQ12 modifies the instruction, its state
is equivalent to the /W line during the execution of a
control state under Hardware control. If the instruction
calls for a data transaction on the DQ31–0 lines, then it is
latched into the Instruction register but no further action
takes place during that cycle. Subsequent Data Read or
Write cycles with the /AV line LOW will cause the
instruction to be executed with the data on the DQ31–0
lines.
The table is accessed during a Compare cycle. The single
bit that is accessed in the VP Table by the address formed
from Comparison data bits 31–20 is used to indicate
whether there is a VP Table match at that address. The
A Read cycle with the /AV line HIGH will access the
Status register, allowing results to be read back without
Rev. 3
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