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MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C4320L ATMCAM  
Operational Characteristics  
PA3–0:AA11–0 After a Write at Next Free Address  
Cycle  
PA3–0:AA11–0 Conditions of Operation  
During a control state that does not have any effect on  
the device address, such as a Write Register cycle, the  
PA3–0:AA11–0 lines remain unchanged. In other  
words, the state of the PA3–0:AA11–0 lines persists  
until another cycle causes it to change.  
After  
a Write at Next Free Address cycle the  
PA3–0:AA11–0 lines carry the address that was written to  
during that cycle. Only the device in which the write  
occurred enables its PA3–0:AA11–0 lines. All other  
devices keep their PA3–0:AA11–0 lines in high  
impedance regardless of the state of their /OE inputs.  
When enabled by /OE being LOW, the  
PA3–0:AA11–0 lines are only free to change while /E  
is HIGH. When /E goes LOW the PA3–0:AA11–0  
lines are latched.  
In the event that the system was full prior to the Write at  
Next Free Address cycle being executed, so that the write  
operation was suppressed, the PA3–0:AA11–0 lines carry  
all 1s. The lowest-priority device, as indicated by bit FR25  
in the Configuration register, enables its PA3–0:AA11–0  
lines and provides the source of all 1s. All other devices  
keep their PA3–0:AA11–0 lines in high impedance  
regardless of the state of their /OE inputs.  
The PA3–0:AA11–0 lines are enabled when /OE is  
LOW provided that the previous cycle causes them to  
be active. When /OE is HIGH, the PA3–0:AA11–0  
lines are in high impedance. Note that /OE is  
asynchronous with respect to /E, and is independent  
of Chip Select from either /CS1, /CS2, or through the  
Device Select register, except in the case of  
non-broadcast random Read and Write cycles to the  
CAM.  
PA3–0:AA11–0 After a Random Access Read or Write  
to the CAM  
After a random Read or Write cycle to the CAM, the  
PA3–0:AA11–0 lines carry the address that was accessed  
during that cycle. Only the device in which the access  
occurred enables its PA3–0:AA11–0 lines. All other  
devices keep their PA3–0:AA11–0 lines in high  
impedance regardless of the state of their /OE inputs. Note  
that the access to the PA3–0:AA11–0 bus differs in this  
respect from the operation of the Status register which is  
accessible in any selected device under this particular  
circumstance.  
PA3–0:AA11–0 and the Match Flags  
The Match flags /MV, /MF, /MM reflect the results of the  
most recent Comparison cycle. During a Comparison  
cycle, they do not change until after /E has gone HIGH  
after which they are free to change combinatorially; their  
state is not latched when /E is LOW. This condition allows  
some pipelining to occur and is useful in systems with  
long daisy chains. A Comparison cycle can be followed by  
another cycle that does not affect the PA3–0:AA11–0 lines  
before the daisy chain is resolved. For example:  
In the event that the Write cycle was broadcast to multiple  
devices, all devices that have their /OE lines held LOW  
will enable their PA3–0:AA11–0 lines. Under this  
circumstance, it is up to the system designer to ensure that  
only one /OE line is driven LOW to prevent bus  
contention on the PA3–0:AA11–0 lines.  
CMP CR  
WR CR  
The WR CR control state can be executed before the daisy  
chain has resolved device prioritization after the CMP CR  
control state. The /OE is then asserted at a suitable time,  
depending on the length of the daisy chain. The Match  
address of the highest-priority responding device is then  
driven onto the PA3–0:AA11–0 lines.  
PA3–0:AA11–0 After a Random Access Read or Write  
to the VP Table  
After a Read or Write cycle to the VP Table, the  
PA3–0:AA11–0 lines carry the address of the location  
accessed in the VP Table. The VP Table is held in the  
lowest-priority device, which therefore is the only device  
to enable its PA3–0:AA11–0 lines. All other devices keep  
their PA3–0:AA11–0 lines in high impedance regardless  
of the state of their /OE inputs.  
The /MV, /MF, /MM lines continue to indicate the results  
of the most recent match, even when the PA3–0:AA11–0  
lines carry an address other than the Match address. This  
condition allows rapid return to the Match address value  
on the PA3–0:AA11–0 lines through a RD[HPM] cycle,  
without the daisy chain having to re-resolve device-level  
prioritization.  
12  
Rev. 3  
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