MU9C4320L ATMCAM
Pin Descriptions
/FF (Full Flag, Output)
/MV (Match Valid, Output)
The /FF output indicates when all the memory locations
have their Validity bits set valid (LOW). When there is at
least one location with its Validity bit set HIGH, the /FF
output will be HIGH; when all locations have their
Validity bits set LOW, and the /FI input is LOW, the /FF
output will be LOW. If the /FI input is HIGH, the /FF
output will be HIGH. The state of the /FF line will not
change until after the rising edge of /E during a Write
cycle.
After a Compare cycle, the /MV line indicates whether
there has been a valid match in this device in either the
CAM array or the VP Table. When /MV is LOW then a
match has occurred in either the CAM array or the VP
Table; when /MV is HIGH then a mismatch has occurred
in both the CAM array and the VP Table. The /MF output
is used to distinguish between the two types of matches.
The state of the /MV line will not change until after the
rising edge of /E during a Comparison cycle. /MV
represents local conditions written in the device; it is not
conditioned by the /MI input.
/FI (Full Input, Input)
The /FI input receives full information from the next
higher-priority ATMCAM in a vertically cascaded system
to provide system-level full information. When the /FI
input is LOW the /FF output will be HIGH if there is at
least one location whose Validity bit is set invalid; when
all locations have their Validity bits set valid, the /FF
output goes LOW. When the /FI input is HIGH, the /FF
output will remain HIGH. The /FF output from one device
is connected to the /FI input of the next lower-priority
device to give system-full indication. The /FI pin of the
highest-priority device must be tied LOW.
/RESET
The /RESET input is used to reset the ATMCAM to a
known state. When the /RESET line is pulled LOW it
causes the ATMCAM to enter its reset state. After power
is applied to the ATMCAM, the /RESET line must be held
LOW for a time equal to or greater than the minimum
RESET pulse width before the device can operate
correctly.
TCLK (JTAG Test Clock, Input)
The TCLK input is the Test Clock input.
/MM (Multiple Match, Open Drain Output)
TMS (JTAG Test Mode Select, Input)
The /MM line indicates that there is a multiple match
within the system. When the /MI input is HIGH, the /MM
line is pulled LOW if there are at least two matches within
the ATMCAM as a result of the previous Comparison
cycle; when there are less than two matches, the /MM line
floats HIGH. When the /MI input is LOW, the /MM line is
pulled LOW if there are one or more matches within the
ATMCAM as a result of the previous Comparison cycle;
when there are no matches, the /MM line floats HIGH.
The /MM lines have open-drain outputs, so all /MM lines
within the system are connected together to give
system-level multiple match indication. The state of the
/MM line will not change until after the rising edge of /E
during a Comparison cycle. The /MM line is unaffected by
matches in the VP Table.
The TMS input is the Test Mode Select input.
TDI (JTAG Test Data Input, Input)
The TDI input is the Test Data input.
TDO (JTAG Test Data Output, Output)
The TCLK output is the Test Data output.
/TRST (JTAG Reset, Input)
The /TRST input is the Reset input, and serves to reset the
Test Access Port circuitry to its reset condition.
VDD, GND (Positive Power Supply, Ground)
These pins are the main power supply connections to the
ATMCAM. VDD must be held at +3.3 Volt ± 0.3 Volt
relative to the GND pin, which is at 0 Volt, system
reference potential, for correct operation of the device.
Note: The TCLK, TMS, TDI, TDO, and /TRST lines are defined
in the IEEE Standard Test Access Port and Boundary-scan
Architecture IEEE Std. 1149.1-1990 and IEEE Std.
1149.1a-1993.
6
Rev. 3
MUSIC [ MUSIC SEMICONDUCTORS ]
