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MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Operational Characteristics  
MU9C4320L ATMCAM  
Software Control  
Active Address Interface PA3–0:AA11–0  
For optimum performance, the ATMCAM is controlled  
through the AC11–0 lines, allowing data transactions  
through the DQ31–0 lines during a control cycle. In cases  
where the overhead of a separate data load cycle can be  
accommodated, the ATMCAM can be operated through  
the Instruction register.  
The Active Address interface PA3–0:AA11–0 carries the  
currently active address. The address source depends on  
the most recent control state that caused it to change. The  
possible address sources that are output on  
PA3–0:AA11–0 are: Highest-Priority CAM Match  
address, VP Table Match address, Next Free address,  
CAM Read address, CAM Write address, VP Table Read  
address, and VP Table Write address.  
Control through the Instruction register is selected by the  
FR27–26 bits of the Configuration register being set  
HIGH. Under this circumstance, the AC11–0 lines are not  
used, instead the instruction is loaded from the DQ11–0  
lines into the Instruction register during a Write cycle with  
the /AV line HIGH. The instructions are directly  
analogous to the control states for any operation that does  
not involve data transfer on the DQ31–0 lines, in which  
case the instruction is executed during the same cycle as  
the instruction is loaded. To distinguish between Read and  
Write control states, DQ12 is used to indicate which type  
of instruction should be executed. When DQ12 is LOW at  
the beginning of the cycle, the instruction executed is the  
Write Cycle instruction (/W = LOW when control state is  
conveyed on AC11–0); when DQ12 is HIGH at the  
beginning of the cycle, the instruction executed is the  
Read Cycle instruction (/W = HIGH when control state is  
conveyed on AC11–0).  
PA3–0:AA11–0 After a Comparison Cycle  
After  
a
Comparison cycle, or access to the  
Highest-Priority address, the PA3–0:AA11–0 lines carry  
one of three possible results:  
The CAM Match address if the Comparison cycle  
resulted in a match in the CAM. Only the device  
containing the highest-priority match enables its  
PA3–0:AA11–0 lines. All other devices with either no  
match or a lower-priority match, as indicated by the  
Match Flag daisy chain, keep their PA3–0:AA11–0  
lines in high impedance regardless of the state of their  
/OE inputs.  
The VP Table Match address if the Comparison cycle  
resulted in a mismatch in the CAM but a match in the  
VP Table. Only the lowest-priority device, as  
indicated by bit FR25 in the Configuration register,  
enables its PA3–0:AA11–0 lines. All other devices  
keep their PA3–0:AA11–0 lines in high impedance  
regardless of the state of their /OE inputs.  
When the instruction calls for data to be written or read  
from the DQ31–0 lines, the instruction is loaded into the  
Instruction register during the cycle, and the next Data  
Read or Write cycle with /AV LOW executes the  
instruction using the DQ31–0 bus for the data transaction.  
The instruction is persistent; i.e., if no other instruction is  
loaded into the Instruction Register, subsequent data  
transactions with the /AV line LOW will be executed  
according to the instruction currently loaded in the  
Instruction register. When there is a data access to a  
memory location on DQ31–0 associated with the  
instruction, the /VB line carries the validity of that  
location.  
All 1s if there was no match in either CAM or VP  
Table, or there was no match in the CAM and the VP  
Table was disabled by Configuration register bit FR24  
being HIGH. The lowest-priority device, as indicated  
by bit FR25 in the Configuration register, enables its  
PA3–0:AA11–0 lines and provides the source of all  
1s. All other devices will keep their PA3–0:AA11–0  
lines in high impedance regardless of the state of their  
/OE inputs.  
Instructions that involve data transactions on DQ31–0, and  
are therefore executed on a subsequent Read or Write  
cycle with the /AV line LOW, are all Read/Write Memory  
and Read/Write Register instructions, Read Validity, Write  
DQ3–0 to PA in Configuration register of Highest-Priority  
Empty device, and Set /FF. All other instructions are  
executed in a single cycle with the state of DQ12 being  
interpreted as the state of the /W line during the equivalent  
hardware control state. A Read cycle with /AV HIGH  
accesses the Status register.  
Rev. 3  
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