Functional Description
MU9C4320L ATMCAM
FUNCTIONAL DESCRIPTION
Data is read from and written to the ATMCAM through
the DQ31–0 lines. The ATMCAM is controlled through
the Control bus, which comprises Chip Enable (/E), two
Chip Selects (/CS1, /CS2), Write Enable (/W), Output
Enable (/OE), Validity Bit Control (/VB), Address Valid
(/AV), and Address/Control inputs (AC11–0). When the
/AV line is LOW, the AC11–0 lines carry an address for
random access into the Memory array; when it is HIGH,
the AC11–0 lines convey control information. The
ATMCAM control states perform Read/Write Memory,
Read/Write Register, Data Move, Comparison, Set
Validity, VP Table Control, and Initialization. These
functions are summarized in Table 1 on page 19.
Random access to memory locations occurs when the /AV
line is LOW; during a Write cycle, the validity of the
location is set by the /VB input. When the /AV line is
HIGH the control states allow read and write access to the
register set comprising Comparand register, seven mask
registers, a Configuration register, a Status register, an
Address register, a Device Select register, and an
Instruction register. The Configuration register sets the
persistent operating conditions of the device: the Page
address of the device, selection of mask register for
directly addressed memory writes, selection between
hardware and software control, enabling VP Table lookup,
selection of VP Table masking, and VP Table Page
address.
When Hardware control is selected, control is through the
AC11–0 bus. When software control is selected, control is
through the Instruction register, which is loaded from the
DQ bus. Under software control the /AV line is used to
distinguish between data and an instruction on the DQ bus.
Therefore, in Software Control mode, random access to
the Memory array can only take place through indirect
addressing using the Address register.
The two Chip Select lines /CS1, /CS2 enable the device
and simplify access to a multi-chip system, if either Chip
Select line is LOW the device is selected. The ATMCAM
also can be selected through the Device Select register
when its value is set to that of the Page address of the
device, and the enable bit in the Device Select register is
set LOW. The /OE input enables the output signals and is
used to synchronize devices in a multi-chip system, and to
prevent race conditions between devices during priority
resolution.
The output signals comprise the Active address (AA11–0),
and the Page address (PA3–0). The PA3–0:AA11–0 bus
carries the current Active address which is either the
Match address, VP Table address, Next Free address, or
the Random Access address, concatenated with the Device
Rev. 3
Page address. The source of Active address is dependent
on the previous control state, allowing access to associated
data in the external RAM at the same location as an access
in the ATMCAM for all types of cycles.
The Output Enable /OE controls the PA3–0:AA11–0 bus:
when it is LOW after a Compare cycle, the
highest-priority responding device outputs its Page and
Match addresses on PA3–0:AA11–0. Only the
highest-priority responding device is enabled, all other
lower-priority devices will have their PA3–0:AA11–0
lines in their high-impedance state, regardless of the state
of their respective /OE lines; when /OE is HIGH, the
PA3–0:AA11–0 lines remain in their high-impedance
state.
When a mismatch occurs in the system, the lowest-priority
device, as defined in the Configuration register, will drive
the PA3–0:AA11–0 bus with all 1s. When any Read or
Write cycle occurs, the address of the accessed location is
output on the PA3–0:AA11–0 bus. The address output on
the PA3–0:AA11–0 bus is persistent, and is held latched
until /E goes HIGH during the next cycle that changes the
Active address. The PA3–0:AA11–0 lines are free to
change only while /E is HIGH. Once /E goes LOW, the
state of the PA3–0:AA11–0 bus is latched.
After a Compare cycle, the /MV, /MF, and /MM flags are
free to change after /E has gone HIGH. Once the Match
Flag daisy chain has resolved device prioritization, the
/OE lines can be asserted to enable the PA3–0:AA11–0
lines from the highest-priority matching device.
In a multi-CAM system, when a device remains deselected
during a Compare cycle through /CS1 and /CS2 being
HIGH and there being no match between the Device
Select register and the Page Address register that device
will clear any previous positive match results. In other
words, if it had previously been indicating a match from
an earlier Comparison cycle, it will now be set to indicate
a mismatch, even though it was not selected during the
most recent Compare cycle.
For pure software control of the ATMCAM, instructions
can be loaded into the Instruction register, and results read
from the Status register. The Status register holds the
results of comparison: PA3–0:AA11–0, /MF, /FF, /MV,
and /MM plus two PA:AA Validation bits which indicate
the type of cycle that generated the PA3–0:AA11–0 value.
The ATMCAM supports VP Table lookup in parallel with
VPI/VCI comparison in the CAM array. This option is
selected through the Configuration register. When active,
Comparand Register bits CR31–20 are used to address the
4K x 1 VP Table simultaneously with the Compare cycle.
7
MUSIC [ MUSIC SEMICONDUCTORS ]
