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MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Register Descriptions  
MU9C4320L ATMCAM  
PA3–0:AA11–0 and the Status Register  
The Status Register bits SR15–0 reflect the  
PA3–0:AA11–0 lines under all conditions. The Status  
Register flags /MV, /MF, /MM, and /FF represent the local  
conditions within the device, and are not conditioned by  
the /MI and /FI inputs.  
active PA3–0:AA11–0 lines. In the case of a random  
access Read or Write cycle, the Status register of any  
selected device can be accessed by a Read Status Register  
cycle. The system designer must ensure that a Status  
Register Read cycle after a random Read or Write cycle is  
into a single device using Chip Select /CS1, /CS2, or the  
Device Select register to prevent bus contention on the  
DQ31–0 bus.  
After a Comparison cycle, Write at Next Free address, or  
access to the Highest-Priority Matching device, a Status  
Register Read cycle is executed in the same device as the  
REGISTER DESCRIPTIONS  
Configuration Register  
The register set contains a Comparand register, seven  
mask registers, Address register, Configuration register,  
Status register, Next Free Address register, Device Select  
register, and Instruction register. Note that all RESERVED  
bits can be read and written without affecting the operation  
of the device. However, for forward compatibility with  
future product enhancements, system designers should not  
rely on any particular RESERVED bit having no effect on  
the operation of the device in future revisions. Therefore,  
all RESERVED bits should be set to logical zero.  
The 32-bit Configuration register sets the persistent  
operating conditions of the ATMCAM. Bits FR31–29  
select which mask register is used for direct Write cycles  
to the CAM array when the address is conveyed on the  
AC11–0 lines (/AV=LOW), a value of 000 in this field  
results in unmasked direct Write cycles. Bits FR27–26  
select the mode of operation: Hardware Control mode or  
Software Control mode. Bit FR25 is used to identify the  
lowest priority device in a vertically cascaded system. Bit  
24 is used to enable or disable the VP Table in the  
lowest-priority device. Bits FR23–12 hold the VP Table  
Address mask. Bits FR7–4 hold the VP Table Page  
address. Bits FR3–0 hold the device Page address. All  
other bits are reserved and should be set LOW. See Table 3  
on page 26.  
Comparand Register  
The 32-bit Comparand register holds the value to be  
compared with the valid contents of the CAM array,  
although the DQ lines can be compared directly, and then  
optionally written into the Comparand register.  
Mask Registers  
Status Register  
There are seven 32-bit mask registers which are used to  
mask Compare and Write cycles. When a bit is set LOW in  
a selected mask register, the corresponding bit enters into  
comparison during a Compare cycle, or is written during a  
Write cycle. When a bit is set HIGH in a selected mask  
register, the corresponding bit does not enter into  
The 32-bit Status register holds the results of the most  
recent control state that caused the PA:AA lines to change.  
It is intended for use in Software Control mode where  
results of an operation are read from the CAM through the  
DQ31–0 lines. Bit SR31 holds the Match Valid flag, /MV,  
which goes LOW if there is a match in the CAM array or a  
hit in the VP Table. Bit SR31 holds the Match flag, /MF,  
which goes LOW when there is a match in the CAM array.  
Bit SR29 holds an internal version of the Multiple Match  
flag, /MM, which is LOW if there is a multiple match in  
the particular device; note that this is not a system-level  
multiple match indication. Bit SR28 holds the Full flag,  
/FF, which goes LOW when all the CAM array locations  
are set valid, and the /FI line is LOW. Bits SR25–24  
indicate the type of result held in the Active Address field:  
Match address, Memory Access address, VP Table  
address, or Reset state. Bits SR19–16 hold the Page  
address, PA3–0, for the device. Bits SR11–0 hold the  
Active address, AA11–0. All other bits are reserved and  
are set LOW. See Table 4 on page 26.  
comparison during  
a Compare cycle, or remains  
unchanged after a Write cycle.  
Address Register  
The 32-bit Address register is used for indirect addressing  
of the CAM array. When random access to the CAM array  
is restricted to indirect addressing, the width of the control  
bus can be reduced to 9 bits if masking is used or 6 bits if  
it is not. Control states allow increment and decrement of  
the Address register as well as auto-increment and  
auto-decrement Read and Write cycles. Bits AR11–0 hold  
the address while bits AR31–12 are reserved and should  
be set LOW.  
Rev. 3  
13  
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