欢迎访问ic37.com |
会员登录 免费注册
发布采购

MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
 浏览型号MU9C4320L-70TDI的Datasheet PDF文件第19页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第20页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第21页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第22页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第24页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第25页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第26页浏览型号MU9C4320L-70TDI的Datasheet PDF文件第27页  
Control State Descriptions  
MU9C4320L ATMCAM  
Control State:  
Mnemonic:  
Move Data from Comparand  
Register to Next Free Address  
MOV [NFA],CR{MRnnn}  
Comparison  
Control State:  
Compare Comparand Register  
with Memory Array  
CMP CR,{MRnnn}  
Binary Op Code: XXX nnn 001 101  
Mnemonic:  
/W: LOW /AV: HIGH PA:AA: NFA Scope: NFD  
Description: Moves data from the Comparand Register to  
the Next Free address. In a vertically cascaded system, the  
write will take place in the device whose /FI=LOW and  
/FF=HIGH, and at the highest-priority location whose  
Validity bit is set HIGH. The validity of the location is set  
by the state of the /VB input, /VB = LOW: Valid, /VB =  
HIGH: Empty. The move is masked by the contents of  
Mask Register nnn. When nnn=000 no mask is used; when  
masking is selected, only bits in the addressed location  
that correspond to LOW values in the selected mask  
register are updated.  
Binary Op Code: XXX nnn 011 000  
/W: LOW /AV: HIGH PA:AA: HPMA Scope: AS  
Description: The Comparand register is compared with  
all locations in the Memory array that have their Validity  
bits set LOW. The comparison is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits that correspond to  
LOW values in the selected mask register are compared.  
Control State:  
Compare Data Bus with  
Memory Array  
Mnemonic:  
CMP DQ,{MRnnn}  
Binary Op Code: XXX nnn 011 001  
Control State:  
Move Data from Comparand  
Register to Highest-Priority  
Matching Location  
/W: LOW /AV: HIGH PA:AA: HPMA Scope: AS  
Description: The data from the DQ bus is compared with  
all locations in the Memory array that have their Validity  
bits set LOW. The comparison is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits that correspond to  
LOW values in the selected mask register are compared.  
Mnemonic:  
MOV [HPM],CR{MRnnn}  
Binary Op Code: XXX nnn 001 110  
/W: LOW /AV: HIGH PA:AA: HPMA Scope: HPD  
Description: Moves data from the Comparand register to  
the Highest-Priority Matching address from the previous  
Comparison cycle. The validity of the location is set by the  
state of the /VB input, /VB = LOW: Valid, /VB = HIGH:  
Empty. The move is masked by the contents of Mask  
Register nnn. When nnn=000 no mask is used; when  
masking is selected, only bits in the addressed location  
that correspond to LOW values in the selected mask  
register are updated.  
Control State:  
Compare Data Bus with Memory  
Array; Write Data Bus to  
Comparand Register  
Mnemonic:  
CMPW DQ,{MRnnn}  
Binary Op Code: XXX nnn 011 010  
/W: LOW /AV: HIGH PA:AA: HPMA Scope: AS  
Description: The data from the DQ bus is compared with  
all locations in the Memory array that have their Validity  
bits set LOW. The data from the DQ31–0 bus is written to  
the Comparand register. The comparison is masked by the  
contents of Mask Register nnn. When nnn=000 no mask is  
used; when masking is selected, only bits that correspond  
to LOW values in the selected mask register are compared.  
Note that the selected mask register masks the comparison  
and not the write to Comparand register.  
Control State:  
Move Data from Highest-Priority  
Matching Location to  
Comparand Register  
Mnemonic:  
MOV CR,[HPM]{MRnnn}  
Binary Op Code: XXX nnn 001 110  
/W: HIGH /AV: HIGH PA:AA: HPMA Scope: HPD  
Description: Moves data from the Highest-Priority Match  
address from the previous Comparison cycle to the  
Comparand register. The move is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated. Note that the /VB line is not  
driven during this operation.  
Control State:  
Mnemonic:  
Advance to Next Matching Location  
INC MA  
Binary Op Code: XXX nnn 011 011  
/W: LOW /AV: HIGH PA:AA: HPMA Scope: HPD  
Description: Advances the Match address to the next  
matching location when the previous Comparison cycle  
resulted in a multiple match. The /MF flag will go HIGH  
when all matches have been exhausted, therefore the  
scheme operates in vertically cascaded systems through  
the priority daisy chain.  
Rev. 3  
23  
 复制成功!