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MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C4320L ATMCAM  
Control State Descriptions  
CONTROL STATE DESCRIPTIONS  
Control State:  
Mnemonic:  
Binary Op Code: XXX nnn 000 000  
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S  
Description: Reads data from the location defined by the  
contents of the Address register to the DQ31–0 bus. This  
control state provides indirect random access memory  
reads. During the Read cycle, the /VB line carries the  
Validity bit value of the addressed location.  
Indirect Read at Address  
RD[AR]  
Read/Write Memory  
Control State:  
Mnemonic:  
Direct Write at Address  
WR[aaa]  
Binary Op Code: aaa  
/W: LOW /AV: LOW PA:AA: aaa Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
location defined by the address value present on the  
AC11–0 bus. The write optionally can be masked by the  
mask register selected through the Configuration register;  
when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated. The validity of the location is  
set by the state of the /VB input, /VB = LOW: Valid, /VB  
= HIGH: Empty. This control state provides direct random  
access memory writes. This control state, along with the  
Read cycle equivalent is the only one that uses direct  
addressing. It is selected by the /AV line being LOW. All  
other control states have the /AV line HIGH whereby the  
AC11–0 bus carries a control code. This control state is  
not available in software mode.  
Control State:  
Indirect Write at Address;  
Increment Address Register  
WR[AR]+{MRnnn}  
Mnemonic:  
Binary Op Code: XXX nnn 100 110  
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
location defined by the contents of the Address register.  
The validity of the location is set by the state of the /VB  
input, /VB = LOW: Valid, /VB = HIGH: Empty. The write  
is masked by the contents of Mask Register nnn. When  
nnn=000 no mask is used; when masking is selected, only  
bits in the addressed location that correspond to LOW  
values in the selected mask register are updated. The  
contents of the Address register are incremented.  
Control State:  
Mnemonic:  
Direct Read at Address  
RD[aaa]  
Binary Op Code: aaa  
Control State:  
Indirect Read at Address;  
Increment Address Register  
RD[AR]+  
/W: HIGH /AV: LOW PA:AA: aaa Scope: S  
Description: Reads data from the location defined by the  
address value present on the AC11–0 bus to the DQ31–0  
bus. This control state provides direct random access  
memory reads. This control state, along with the Write  
cycle equivalent is the only one that uses direct  
addressing. It is selected by the /AV line being LOW. All  
other control states have the /AV line HIGH whereby the  
AC11–0 bus carries a control code. During the Read cycle,  
the /VB line carries the Validity Bit value of the addressed  
location. This control state is not available in software  
mode.  
Mnemonic:  
Binary Op Code: XXX XXX 100 110  
/W: HIGH /AV: HIGH PA:AA: aaa Scope: AS  
Description: Reads data from the location defined by the  
contents of the Address register to the DQ31–0 bus. This  
control state provides indirect random access memory  
reads. During the Read cycle, the /VB line carries the  
Validity Bit value of the addressed location. The contents  
of the Address register are incremented.  
Control State:  
Indirect Write at Address;  
Decrement Address Register  
WR[AR]-{MRnnn}  
Control State:  
Mnemonic:  
Indirect Write at Address  
WR[AR]{MRnnn}  
Mnemonic:  
Binary Op Code: XXX nnn 100 111  
Binary Op Code: XXX nnn 000 000  
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
location defined by the contents of the Address register.  
The validity of the location is set by the state of the /VB  
input, /VB = LOW: Valid, /VB = HIGH: Empty. The write  
is masked by the contents of Mask Register nnn. When  
nnn=000 no mask is used; when masking is selected, only  
bits in the addressed location that correspond to LOW  
values in the selected mask register are updated. The  
contents of the Address register are decremented.  
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
location defined by the contents of the Address register.  
The validity of the location is set by the state of the /VB  
input, /VB = LOW: Valid, /VB = HIGH: Empty. The write  
is masked by the contents of Mask Register nnn. When  
nnn=000 no mask is used; when masking is selected, only  
bits in the addressed location that correspond to LOW  
values in the selected mask register are updated. This  
control state provides indirect random access memory  
writes.  
20  
Rev. 3  
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