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MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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Control State Descriptions  
MU9C4320L ATMCAM  
Read Highest-Priority  
Matching Location  
RD[HPM]  
Control State:  
Mnemonic:  
Indirect Read at Address;  
Decrement Address Register  
RD[AR]  
Control State:  
Mnemonic:  
Binary Op Code: XXX XXX 100 111  
Binary Op Code: XXX XXX 000 010  
/W: HIGH /AV: HIGH PA:AA: aaa Scope: S  
Description: Reads data from the location defined by the  
contents of the Address register to the DQ31–0 bus. This  
control state provides indirect random access memory  
reads. During the Read cycle, the /VB line carries the  
Validity Bit value of the addressed location. The contents  
of the Address register are decremented.  
/W: HIGH /AV: HIGH PA:AA: HPMA Scope: HPD  
Description: Reads data from the location defined by the  
highest-priority matching location to the DQ31–0 bus. In  
the event that the previous Comparison cycle resulted in a  
mismatch, the DQ31–0 bus will remain in high  
impedance.  
Register Read/Write  
Control State:  
Mnemonic:  
Write at Next Free Address  
WR[NFA]{MRnnn}  
Control State:  
Mnemonic:  
Write Address Register  
WR AR{MRnnn}  
Binary Op Code: XXX nnn 000 001  
Binary Op Code: XXX nnn 000 100  
/W: LOW /AV: HIGH PA:AA: NFA Scope: NFD  
Description: Writes data from the DQ31–0 bus to the next  
free location in the Memory array. In a vertically cascaded  
system, the write will take place in the device whose  
/FI=LOW and /FF=HIGH, and at the highest-priority  
location whose Validity bit is set HIGH. The validity of  
the location is set by the state of the /VB input, /VB =  
LOW: Valid, /VB = HIGH: Empty. The write is masked by  
the contents of Mask Register nnn. When nnn=000 no  
mask is used; when masking is selected, only bits in the  
addressed location that correspond to LOW values in the  
selected mask register are updated.  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
Address register. The write is masked by the contents of  
Mask Register nnn. When nnn=000 no mask is used; when  
masking is selected, only bits in the addressed location  
that correspond to LOW values in the selected mask  
register are updated.  
Control State:  
Mnemonic:  
Read Address Register  
RD AR  
Binary Op Code: XXX XXX 000 100  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Address register to  
the DQ31–0 bus.  
Control State:  
Read Highest-Priority  
Matching Location; Increment  
Match Address  
Control State:  
Mnemonic:  
No Operation  
NOP  
Mnemonic:  
RD[HPM];INC MA  
Binary Op Code: XXX XXX 000 011  
Binary Op Code: XXX XXX 000 001  
/W: LOW /AV: HIGH PA:AA: n/c Scope: n/a  
Description: No operation. The device performs no  
operation during the cycle. No existing states change.  
/W: HIGH /AV: HIGH PA:AA: HPMA Scope: HPD  
Description: Reads data from the location defined by the  
highest-priority matching location to the DQ31–0 bus. In  
the event that the previous Comparison cycle resulted in a  
mismatch, the DQ31–0 bus will remain in high  
impedance. The Next Highest-Priority Matching location  
is selected and its address appears on the PA3–0:AA11–0  
lines.  
Control State:  
Mnemonic:  
Read Next Free Address  
RD NFA  
Binary Op Code: XXX XXX 000 011  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: NFD  
Description: Reads the value of the Next Free address on  
the DQ11–0 bus. In a vertically cascaded system this will  
be in the device whose /FI=LOW and /FF=HIGH, and at  
the highest-priority location whose Validity bit is set  
HIGH. This value is the address of the location where a  
subsequent Write at Next Free Address cycle will be  
written. The Page address of the device value is output on  
DQ15–12; DQ31–16 are LOW.  
Control State:  
Write to Highest-Priority  
Matching Location  
WR[HPM]{MRnnn}  
Mnemonic:  
Binary Op Code: XXX nnn 000 010  
/W: LOW /AV: HIGH PA:AA: HPMA Scope: HPD  
Description: Writes data from the DQ31–0 bus to the  
highest-priority matching location in the Memory array.  
The validity of the location is set by the state of the /VB  
input, /VB=LOW: Valid, /VB=HIGH: Empty. The write is  
masked by the contents of Mask Register nnn. When  
nnn=000 no mask is used; when masking is selected, only  
bits in the addressed location that correspond to LOW  
values in the selected mask register are updated.  
Rev. 3  
21  
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