MU9C4320L ATMCAM
Control State Descriptions
Table 3: Configuration Register Bit Assignments
Bit(s)
Name
Description
31:29
Direct Write Mask Source
000 = No Mask
001 = Mask Register 1
010 = Mask Register 2
011 = Mask Register 3
100 = Mask Register 4
101 = Mask Register 5
110 = Mask Register 6
111 = Mask Register 7
28
Reserved
Set to 0
27:26
Control Mode
00 = Hardware Control Mode
01 = Reserved
10 = Reserved
11 = Software Control Mode. (If /AV = 1, access Status Register.)
25
24
LPC
0 = Low priority CAM
1 = Not low priority CAM
EN VP
0 = Enable VP table
1 = Disable VP table
23:12
11:8
7:4
VP Table Address Mask
VP Table Page Address
Reserved
VP Table Address Mask value
VP Table Page Address value
Set to 0
3:0
Page Address PA3-0
Page Address value
Table 4: Status Register Bit Assignments
Bit(s)
Name
Description
31
/MV
0 = Match in CAM or VP table
1 = No match in CAM or VP table
30
29
28
/MF
/MM
/FF
0 = Match in CAM
1 = No match in CAM
0 = Multiple match in CAM
1 = No multiple match in CAM
0 = Full
1 = Not full
27:26
25:24
Reserved
Set to 0
Active Address Type
00 = Match address
01 = Memory access
10 = VP table address
11 = Reset state
23:20
19:16
15:12
11:0
Reserved
Set to 0
Page Address PA3-0
Reserved
Page Address
Set to 0
Active Address A11-0
Active Address
Table 5: Next Free Register Bit Assignments
Bit(s)
31:20
19:16
15:12
11:0
Name
Description
Set to 0
Reserved
Page Address PA3-0
Reserved
Page Address
Set to 0
Next Free Address NF11-0 Next Free Address
Table 6: Device Select Register Bit Assignments
Bit(s)
31:9
8
Name
Description
Reserved
SELEN
Set to 0
0 = Enable Select
1 = Disable Select
7:4
3:0
Reserved
Set to 0
Device Select DS3-0
Device Select when PA3-0 = DS3-0 and SELEN = 0
26
Rev. 3
MUSIC [ MUSIC SEMICONDUCTORS ]
