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MU9C4320L-70TDI 参数 Datasheet PDF下载

MU9C4320L-70TDI图片预览
型号: MU9C4320L-70TDI
PDF下载: 下载PDF文件 查看货源
内容描述: 4K ×32的内容可寻址存储器(CAM )具有32位宽的数据接口 [4K x 32 Content Addressable Memory (CAM) with a 32-bit wide data interface]
分类和应用: 存储内存集成电路静态存储器双倍数据速率
文件页数/大小: 32 页 / 449 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C4320L ATMCAM  
Control State Descriptions  
Control State:  
Mnemonic:  
Write Configuration Register  
WR FR{MRnnn}  
Control State:  
Mnemonic:  
Read Comparand Register  
RD CR  
Binary Op Code: XXX nnn 000 110  
Binary Op Code: XXX XXX 000 101  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
Configuration register. The write is masked by the  
contents of Mask Register nnn. When nnn=000 no mask is  
used; when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated.  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Comparand  
register to the DQ31–0 bus.  
Control State:  
Mnemonic:  
Write Mask Register  
WR MRnnn  
Binary Op Code: XXX nnn 001 001  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
Mask register. If nnn=000 then no data is written.  
Control State:  
Mnemonic:  
Read Configuration Register  
RD FR  
Binary Op Code: XXX XXX 000 110  
Control State:  
Mnemonic:  
Binary Op Code: XXX nnn 001 001  
Read Mask Register  
RD MRnnn  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Configuration  
register to the DQ31–0 bus.  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Mask register to  
the DQ31–0 bus. If nnn=000 then the output is undefined.  
Control State:  
Mnemonic:  
Binary Op Code: XXX nnn 001 000  
Write Device Select Register  
WR DS{MRnnn}  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
Device Select register. The write is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated.  
Data Move  
Control State:  
Move Data from Comparand  
Register to Memory Indirect  
MOV [AR],CR{MRnnn}  
Mnemonic:  
Binary Op Code: XXX nnn 001 100  
/W: LOW /AV: HIGH PA:AA: aaa Scope: AS  
Description: Moves data from the Comparand register to  
the memory address defined by the contents of the  
Address register. The validity of the location is set by the  
state of the /VB input, /VB = LOW: Valid, /VB = HIGH:  
Empty. The move is masked by the contents of Mask  
Register nnn. When nnn=000 no mask is used; when  
masking is selected, only bits in the addressed location  
that correspond to LOW values in the selected mask  
register are updated.  
Control State:  
Mnemonic:  
Read Device Select Register  
RD CR  
Binary Op Code: XXX XXX 001 000  
/W: HIGH AV: HIGH PA:AA: n/c Scope: S  
Description: Reads the contents of the Device Select  
register to the DQ31–0 bus.  
Control State:  
Mnemonic:  
Read Status Register  
RD SR  
Binary Op Code: XXX XXX 000 111  
Control State:  
Move Data from Memory to  
Comparand Register Indirect  
MOV CR,[AR]{MRnnn}  
/W: HIGH /AV: HIGH PA:AA: n/c Scope: HPD/S  
Description: Reads the contents of the Status register to  
the DQ31–0 bus. After a Comparison or Read/Write at  
Highest-Priority Matching Address cycle only the  
highest-priority device with a match responds to this  
Mnemonic:  
Binary Op Code: XXX nnn 001 100  
/W: HIGH /AV: HIGH PA:AA: aaa Scope: AS  
Description: Moves data from the memory address  
defined by the contents of the Address register to the  
Comparand register. The move is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated. Note that the /VB line is not  
driven during this operation.  
control state; in the event of  
a mismatch, the  
lowest-priority device responds. After a random access  
Read or Write cycle into the Memory array, RD SR will  
take place in any selected device.  
Control State:  
Mnemonic:  
Write Comparand Register  
WR CR{MRnnn}  
Binary Op Code: XXX nnn 000 101  
/W: LOW /AV: HIGH PA:AA: n/c Scope: AS  
Description: Writes data from the DQ31–0 bus to the  
Comparand register. The write is masked by the contents  
of Mask Register nnn. When nnn=000 no mask is used;  
when masking is selected, only bits in the addressed  
location that correspond to LOW values in the selected  
mask register are updated.  
22  
Rev. 3  
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