MU9C4320L ATMCAM
Register Descriptions
FULL Cascading
entire system; only the device in which the /MI line is
HIGH and which has a match will respond to the cycle.
This scheme automatically prioritizes a system of
vertically cascaded devices, the highest up in the chain has
the highest priority. Note however, that cycles which do
not access highest-priority match data or the Status
register will operate without regard to the state of the
Match daisy chain.
The Full flag is set LOW in a particular ATMCAM if the
/FI line is LOW, and that device is full. During a Write
cycle, the Full flag will not change until /E goes HIGH
during that cycle. When the /FI line is HIGH, one or more
locations are free in the higher-priority devices; therefore,
when the /FI line is HIGH, whether or not that particular
device is full, its /FF output will remain HIGH. This
method allows the Full Flag daisy chain to recognize
noncontiguous empty locations throughout the entire
ATMCAM system.
Multiple Match Flag Daisy Chain
The Multiple Match flag, /MM is an open-drain output,
and it will be pulled LOW by a particular device when its
/MI input is HIGH and there is more than one match
within the device, or when the /MI input is LOW and there
is one match within the device. During a Comparison
cycle, the Multiple Match flag will not change until /E
goes HIGH during that cycle. This wired-OR output
provides system level indication of the multiple match
The daisy chain gives System Full indication. When the
device at the end of the chain has its /FF output LOW, the
entire CAM system is full. The first device in the daisy
chain has its /FI line tied LOW to ensure data can be
written into the system.
The daisy chain also controls Write at Next Free Address
cycles as well as Read Next Free Address cycles so that
they work globally across the system, and not just locally
in a specific device. Only the device in which the /FI line
is LOW, and which is not full, will respond to the Write
cycle. Therefore, deletions and insertions can be made in
the memory, without the need to keep track of empty
locations.
condition within
ATMCAMs.
a vertically cascaded system of
Match Flag Timing Overhead
There is a propagation delay for the match results to ripple
down through the daisy chain. All the ATMCAMs within
the system execute a Comparison cycle in parallel, so the
local results are available at the end of a Comparison
cycle. The local Match flags do not change during a
Comparison cycle until /E goes HIGH. The logical
combination of the results then propagates down the daisy
chain with a delay through each stage. The compare time
in each device operating in parallel is added to the ripple
delay through the daisy chain. Before reading the results
of a comparison from the System Match flag, the daisy
chain must be given time to settle to a valid state. If there
are N devices vertically cascaded in a system, and the time
to get a valid output on /MF for one device is t(MF), and
the propagation delay for the flag to ripple through one
device from /MI valid to /MF valid is t(PD), then the time
t(DC) for the daisy chain to develop a valid output
condition is:
Match Cascading
The Match flag /MF will be LOW in a particular device
within a vertically cascaded system when its /MI input is
LOW, or when there is a match in that device. During a
Comparison cycle, the Match flag will not change until /E
goes HIGH during that cycle. When the /MI line is LOW,
one or more locations in higher-priority devices have a
match; when the /MI line is LOW, the /MF output will be
forced LOW. This method allows the Match Flag daisy
chain to respond to and prioritize matches throughout the
entire ATMCAM system.
The daisy chaining gives a System Match indication, when
the device at the end of the daisy chain has its /MF output
LOW there is a match within the CAM system. The first
device in the daisy chain has its /MI input tied HIGH.
t(DC) = t(MF) +(N-1) *t(PD)
This period of time must elapse before the flagged results
of the comparison are available, and before /OE is driven
LOW or a Status Register Read cycle is performed.
The daisy chain also controls access to the device by
controlling the outputs during a Read Highest-Priority
Match data, or Read Status register, onto the DQ31–0
lines. The device must be selected with either /CS1, or
/CS2, or the Data Select register. After a Comparison or
Read/Write at Highest-Priority Match Address cycle, only
the device whose /MI line is HIGH, and which has a valid
match, will drive data onto DQ31–0 or onto
PA3–0:AA11–0; any device that has its /MI line set LOW
will have its outputs in their high-impedance state, even if
it has a valid match. Therefore, Reads from and Writes to
the Highest-Priority Matching address operate over the
There is a similar but shorter delay for the Full Flag daisy
chain, but this only limits the rate at which back-to-back
Write at Next Free Address cycles can be performed.
16
Rev. 3
MUSIC [ MUSIC SEMICONDUCTORS ]
