Register Descriptions
MU9C4320L ATMCAM
Device Select Register
that cycle. At this time, the daisy chain starts to resolve
system-level prioritization. Once sufficient time has
elapsed for the daisy chain to be resolved, the
PA3–0:AA11–0 lines can be enabled with /OE, and Status
Register Read cycles will access only the highest-priority
matching device. Note that the daisy chain resolves
system-level prioritization combinatorially once initiated
by /E going HIGH. Other cycles that do not affect the
daisy chain or match results can take place in the
ATMCAM while the daisy chain is resolving, for example,
WR CR, allowing some degree of pipelining. During a
Write cycle, the Full flag will not change until /E goes
HIGH during that cycle.
One dedicated line is needed per device to do local
selection of one device within a multi-CAM system. In
cases where control lines are at a premium, the Device
Select register can be used as the method of selection. If
Device Select Register bit DS8 is LOW, only the device or
devices whose Page Address value, held in Configuration
Register bits FR3-0, match with the Device Select
Register bits DS3–0 will be selected. Note that the match
condition of the Device Select register is ORed with the
state of the /CS1 and /CS2 lines. If DS8 is HIGH, the
device remains unselected through the Device Select
register.
The conditions of the Device Select register, the /CS1 and
/CS2 lines are sampled at the time of the falling edge of /E.
In a particular ATMCAM within a system, that CAM will
be selected under the following conditions:
There is a small propagation delay per device in the daisy
chain. Alternatively, vertical cascading can be done with
external logic that provides prioritization and select lines
back into each device. The ATMCAM architecture
supports external prioritization for cases where the daisy
chain overhead proves unacceptable. Figure 4 shows a
system in which a number of ATMCAMs are vertically
cascaded.
(/CS1=LOW) OR (/CS2=LOW)
OR ((DS8 = LOW) AND (DS3–0 = PA3–0))
Therefore, the /CS1 lines of all devices are tied together
for global cycles that broadcast control states to all devices
within the system; then, for local cycles, an individual
device is selected by loading all the Device Select
Registers bit DS8 LOW and bits DS3–0 with the Page
Address value of the device to be selected. On a
subsequent cycle, /CS1 and /CS2 remain HIGH, and only
the device whose Page Address value matches with its
DS3–0 will respond. After an individual device has been
selected, a global Write cycle to the Device Select register
using /CS1 line is executed to select another device, or to
disable the software chip select mechanism altogether.
'1'
/MI
/MF
'0'
+3.3V
/FI
/MV
/MM
ATMCAM
(Highest Priority)
/FF
/MI
/FI
/MV
/MM
ATMCAM
/FF
Vertical Cascading
/MF
A system can be designed to any practical depth by
vertically cascading ATMCAMs. The scheme uses a daisy
chain to provide system level prioritization as well as
Match, Multiple Match, and Full flags. There are three
daisy chains: Match, Multiple match, and Full, plus a
Match Valid line indicates both the CAM and VP Table
matches.
Lowest Priority
CAM or VP Table
Match
/MI
/MF
/FI
/MV
/MM
ATMCAM
(Lowest Priority)
When a control state is broadcast that accesses the
highest-priority matching location or Status register, the
daisy chain ensures that only the device that responds is
the one with the highest-priority match in the system. All
other devices will have their DQ31–0 lines and
PA3–0:AA11–0 outputs held in high impedance.
Therefore, the Match Flag daisy chain controls access to
the system resources for control states that are conditional
on the results of the previous Compare cycle.
/FF
CAM
Match
Full
Multiple-match
Figure 4: Vertically Cascading ATMCAMs
During a Comparison cycle, the Match and Multiple
Match flags will not change until /E goes HIGH during
Rev. 3
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MUSIC [ MUSIC SEMICONDUCTORS ]
