MU9C1965A/L LANCAM MP
INSTRUCTION SET DESCRIPTIONS Continued
read access. The complete Status register is only available
through a non-TCO Command Read access. Reading the
PS register also outputs the Device ID on bits 15–4, as
shown in Table 13 on page 23.
Instruction: Special Instructions
Binary Op-Code: 0000 0110 00dd drrr*
ddd
rrr
Target resource
Operation
These instructions are a special set for the “A” or “L”
LANCAM MP to accommodate the added features over
the MU9C1485. Two alternate sets of configuration registers
can be selected by using the Select Foreground and Select
Background Registers instructions. These registers are the
Control, Segment Control, Address, Mask Register 1, and
the PS and PD registers. An RSC instruction resets the
Segment Control register count values for both the
Destination and Source counters to the original Start limits.
The Shift instructions shift the designated register one bit
right or left. The right and left limits for shifting are
determined by the CAM/RAM partitioning set in the Control
register. The Comparand register is a barrel-shifter, and for
the example of a device set to 128 bits of CAM executing a
Shift Comparand Right instruction, bit 0 is moved to bit
127, bit 1 is moved to bit 0, and bit 127 is moved to bit 126.
For a Shift Comparand Left instruction, bit 127 is moved to
bit 0, bit 0 is moved to bit 1, and bit 126 is moved to bit 127.
MR2 acts as a sliding mask, where for a Shift Right
instruction bit 1 is moved to bit 0, while bit 0 “falls off the
end,” and bit 127 is replicated to bit 126. For a Shift Mask
Left instruction, bit 0 is replicated to bit 1, bit 126 is moved
to bit 127, and bit 127 “falls off the end.” With shorter width
CAM fields, the bit limits on the right or left move to match
the width of CAM field.
Instruction: Data Move (MOV)
Binary Op-Code: 0000 f011 mmdd dsss* or
0000 f011 mmdd dvss*
f
Address Field flag†
Mask Register select
Destination of data
Source of data
Validity setting if destination is a
Memory location
mm
ddd
sss
v
The MOV instruction performs a 128-bit move of the data
in the selected source to the selected destination. If the
source or destination is aaaH, the Address register is set to
aaaH. For MOV instructions to or from aaaH or [AR], the
Address register will increment or decrement from that value
after the move completes, as set in the Control register.
Data transfers between the Memory array and the
Comparand register may be masked by either Mask Register
1 or Mask Register 2, in which case, only those bits in the
destination which correspond to bits in the selected mask
register set to 0 will be changed. A Memory location used
as a destination for a MOV instruction may be set to Valid
or left unchanged. If the source and destination are the
same register, no net change occurs (a NOP).
Instruction: Validity Bit Control (VBC)
Binary Op-Code: 0000 f100 00dd dvvv*
Instruction: Set Full Flag (SFF)
f
Address Field flag†
Destination of data
Validity setting for Memory location
Binary Op-Code: 0000 0111 0000 0000*
The SFF instruction is a special instruction used to force
the Full flag LOW to permit setting the Page Address
register in vertically cascaded systems.
ddd
vvv
The VBC instruction sets the Validity bits at the selected
memory locations to the selected state. This feature can be
used to find all valid entries by using a repetitive sequence
of CMP V through a mask of all 1s followed by a VBC HM,
S. If the VBC target is aaaH, the Address register is set to
aaaH. For VBC instructions to or from aaaH or [AR], the
Address register will increment or decrement from that value
after the operation completes, as set in the Control register.
Notes:
§ Instruction cycle lengths given in Table 8 on page 22.
* Instruction Op-Codes are loaded on the DQ31–16
lines.
† If f=1, the instruction requires an absolute address
(or register contents for TCOs) to be supplied on
the DQ15–0 lines. Supplied addresses will update
the Address register to the aaaH value supplied.
During operations involving M@[AR] or M@aaaH,
the Address register will be incremented or
decremented depending on the setting in the
Control register.
Instruction: Compare (CMP)
Binary Op-Code: 0000 0101 0000 0vvv*
vvv
A CMP V, S, or R instruction forces a Comparison of Valid,
Skipped, or Random entries against the Comparand register
through a mask register, if one is selected. During a CMP E
instruction, the compare is only done on the Validity bits
and all data bits are automatically masked.
Validity condition
19
Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
