MU9C1965A/L LANCAM MP
OPERATIONAL CHARACTERISTICS Continued
manner filling all the PA registers in turn. Each device must
have a unique Page Address value stored in its PA register,
or contention will result. After all the PA registers are filled,
the entire string is reset through the Control register, which
does not change the values stored in the individual PA
registers. After the reset, the Device Select registers are
usually set to FFFFH to enable operation in Case 1 of Table
6a on page 12. The Control registers and the Segment
Control registers are then set to their normal operating
values for the application.
devices are set for a typical application. Each Page
Address register must contain a unique value (not
FFFFH) to prevent bus contention.
For typical daisy chain operation, data is loaded into the
Comparand registers of all the devices in a string
simultaneously by setting DS=FFFFH. Since reading is
prohibited when DS=FFFFH except for the device with a
match, for a diagnostic operation you need to select a
specific device by setting DS=PA for the desired device
to be able to read from it. Refer to Tables 6a and 6b on
page 12 for preconditions for reading and writing.
Vertically Cascaded System Initialization
Table 7 shows an example of code that initializes a daisy-
chained string of LANCAM MP devices. The
initialization example shows how to set the Page Address
registers of each of the devices in the chain through the
use of the Set Full Flag instruction, and how the Control
registers and Segment counters of all the LANCAM MP
Initialization for a single LANCAM MP is similar. The
Device Select register in this case is usually set to equal
the Page Address register for normal operations. Also,
the dedicated /MA flag output can be used instead of
/MF, allowing /EC to be tied HIGH.
INSTRUCTION SET DESCRIPTIONS§
corresponding to bits in the mask register set to 0 will be
modified. An automatic compare will occur after writing the
last segment of the Comparand or mask registers, but
not after writing to memory. Setting the persistent
destination to M@aaaH loads the Address register with
aaaH, and the first access to that persistent destination
will be at aaaH, after which the AR value increments or
decrements as set in the Control register. The SPD
M@[AR] instruction does the same except the current
Address Register value is used.
Instruction: Select Persistent Source (SPS)
Binary Op-Code: 0000 f000 0000 0sss*
f
Address Field flag†
Selected source
sss
This instruction selects a persistent source for data reads,
until another SPS instruction changes it or a reset occurs.
The default source after reset for Data Read cycles is the
Comparand register. Setting the persistent source to
M@aaaH loads the Address register with aaaH, and the
first access to that persistent source will be at aaaH, after
which the AR value increments or decrements as set in the
Control register. The SPS M@[AR] instruction does the
same except the current Address Register value is used.
Instruction: Temporary Command Override (TCO)
Binary Op-Code: 0000 f010 00dd d000*
f
Address Field flag†
ddd
Register selected as source or
destination for only the next
Command Read or Write cycle
Instruction: Select Persistent Destination (SPD)
Binary Op-Code: 0000 f001 mmdd dvvv*
f
Address Field flag†
The TCO instruction temporarily redirects the DQ bus for
register access. If f=1, a Register write will be performed
with the data on DQ15–0. If f=0, a subsequent Command
Read cycle reads the register contents through DQ15–0.
During register reads, DQ31–16 will contain the upper
16-bits of the Status register, except in the case of a Page
Address Register read where these bits are 0s. After the
access, subsequent Command Read or Write cycles revert
to reading the Status register and writing to the Instruction
decoder. All registers except the Status, NF, PS, and PD are
available for write access. All registers are available for
mm
ddd
vvv
Mask Register select
Selected destination
Validity setting for Memory Location
destinations
This instruction selects a persistent destination for data
writes, which remains until another SPD instruction changes
it or a reset occurs. The default destination for Data Write
cycles is the Comparand register after a reset. When the
destination is the Comparand register or the memory array,
the data written may be masked by either Mask Register 1
or Mask Register 2, so that only destination bits
Rev. 1a
18
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