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MU9C1965L-70TCC 参数 Datasheet PDF下载

MU9C1965L-70TCC图片预览
型号: MU9C1965L-70TCC
PDF下载: 下载PDF文件 查看货源
内容描述: [Content Addressable SRAM, 1KX128, 52ns, CMOS, PQFP80]
分类和应用: 局域网双倍数据速率静态存储器内存集成电路
文件页数/大小: 28 页 / 151 K
品牌: MUSIC [ MUSIC SEMICONDUCTORS ]
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MU9C1965A/L LANCAM MP  
OPERATIONAL CHARACTERISTICS Continued  
automatically masks all 128 bits of data to find all  
locations with the validity bits set to “Empty,” while the  
other forced compares are only masked as selected in  
the Control register.  
/E  
/EC  
VERTICAL CASCADING  
/EC (INT)  
/MF  
LANCAM MPs can be vertically cascaded to increase  
system depth. Through the use of flag daisy-chaining,  
multiple devices will respond as an integrated system.  
The flag daisy chain allows all commands to be issued  
globally, with a response only in the device containing  
the Highest-Priority Matching or Next Free location. When  
connected in a daisy chain, the last device’s Full flag and  
Match flag accurately report the condition for the whole  
string. A system in which LANCAM MPs are vertically  
cascaded using daisy-chaining of the flags is shown in  
Figure 1a on page 7.  
Figure 5: /EC(Int) Timing Diagram  
The minimum timings for the /E control signal are given in  
the Switching Characteristics section on page 26. Note that  
at minimum timings the /E signal is non-symmetrical, and  
that different cycle types have different timing requirements,  
as given in Table 8 on page 22.  
To operate the daisy chain, the Device Select registers are  
set to FFFFH to enable all devices to execute Command  
Write and Data Write cycles. In normal operation, read  
cycles are enabled from the device with the highest-priority  
match by locking the daisy chain (see the “Locked Daisy  
Chain” section). An individual device in the chain may be  
targeted for a read or write operation by temporarily setting  
the Device Select registers to the Page address of the target  
device. Setting the Device Select registers back to FFFFH  
restores the operation of the entire daisy chain.  
COMPARE OPERATIONS  
During a Compare operation, the data in the Comparand  
register is compared to all locations in the Memory array  
simultaneously. Any mask register used during compares  
must be selected beforehand in the Control register. There  
are two ways compares are initiated: Automatic and Forced  
compares.  
Match Flag Cascading  
Automatic compares perform a compare of the contents of the  
Comparand register against Memory locations that are tagged  
as “Valid,” and occur whenever the following happens:  
The Match Flag daisy chain cascading is used for three  
purposes: first, to allow operations on Highest-Priority  
Match addresses to be issued globally over the whole  
string; second, to provide a system wide Match flag;  
third, to lock out all devices except the one with the  
Highest-Priority match for instructions such as Status  
reads after a match. The Match flag logic causes only  
the highest-priority device to operate on its Highest-  
Priority Match location while devices with lower-priority  
matches ignore Highest-Priority Match operations. The  
lock-out feature is enabled by the match flag cascading  
and the use of the /EC control signal, as shown in Tables  
6a and 6b on page 12.  
Ø The Destination Segment counter in the Segment  
Control register reaches its end limit during writes to  
the Comparand or mask registers.  
Ø After a command write of a TCO CT is executed (except  
for a software reset), so that a compare is executed  
with the new settings of the Control register.  
Forced compares are initiated by CMP instructions  
using one of the four validity conditions, V, R, S, and E.  
The forced compare against “Empty” locations  
15  
Rev. 1a  
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