MU9C1965A/L LANCAM MP
REGISTER BIT ASSIGNMENTS Continued
14
DCSL
15
13
10
8
6
5
3
2
1
0
12
11
DCEL
9
7
4
SSL
SCSL
SCEL
LDC
DSCV
LSC
SSCV
SDC
Set
Dest.
Seg.
Limits
= 0
Set
Source
Seg.
Limits
= 0
Load
Dest.
Seg.
Count
= 0
Load
Src.
Seg.
Count
= 0
Destination
Count
End
Limit
00–11
Source
Count
Start
Limit
00–11
Source
Count
End
Limit
00–11
Destination
Seg.
Count
Value
00–11
Source
Seg.
Count
Value
00–11
Destination
Count
Start
Limit
00–11
No
No
No
No
Chng.
= 1
Chng.
= 1
Chng.
= 1
Chng.
= 1
Note: D15, D10, D5, and D2 read back as 0s.
Table 10: Segment Control Register Bit Assignments
31
30
/MM /FL Skip Empty
14 13 12 11
Page Address, PA5–0
29
28
27
26
0
25
9
24
8
23
22
21
20
19
18
2
17
16
0
Page Address Bits, PA15–PA6
/MA
15
10
7
6
5
4
3
1
Next Free Address, NF9–0
Note: The Next Free Address register is read only, and is accessed by performing a Command Read
cycle immediately following a TCO NF instruction.
Table 11: Next Free Address Register Bit Assignments
31
30
29
28
27
26
25
9
24
8
23
22
21
20
19
18
2
17
1
16
0
/FL Skip Empty
Page Address Bits, PA15–PA6
/MM
/MA
0
15
14
13
12
11
10
7
6
5
4
3
PA5–PA0
Match Address, AM9–AM0
Note: The Status register is read only, and is accessed by performing a Command Read cycle.
Table 12: Status Register Bit Assignments
31
30
/MM /FL Skip Empty
14 13 12 11
29
28
27
26
0
25
9
24
8
23
22
21
20
19
18
2
17
16
Page Address Bits, PA15–PA6
/MA
15
10
7
6
5
4
3
1
0
Device ID = 196H
PS
Note: The Persistent Source register is read only, and is accessed by performing a Command Read cycle
immediately following a TCO PS instruction.
Table 13: Persistent Source Register Bit Assignments
23
Rev. 1a
MUSIC [ MUSIC SEMICONDUCTORS ]
