MU9C1965A/L LANCAM MP
INSTRUCTION SET SUMMARY Continued
CYCLETYPE
Command Read
Command Write
CYCLE
Data Write
Data Read
LENGTH
MOV reg, reg
Short
Comparand register
(not last segment)
Mask register
TCO reg (except CT)
TCO CT (non-reset, HMA invalid)
SPS, SPD, SFR
(not last segment)
SBR, RSC, NOP
SFT (A)
MOV reg, mem
TCO CT (reset)
VBC (NFA invalid)
SFT (L)
Medium
Long
Status register or
16-bit register
Memory array
(NFA invalid)
Comparand register
Mask register
MOV mem, reg
TCO CT (non-reset, HMA valid)
Memory array
(NFA valid)
Memory array
CMP
SFF
VBC (NFA valid)
Comparand register
(last segment)
Mask register
(last segment)
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics
Section under the tELEH parameter. For two cycle TCO reads of a register’s contents, the first cycle (Command
Write TCO) is short,and the second cycle (Command Read) is medium.
Table 8: Instruction Cycle Lengths
REGISTER BIT ASSIGNMENTS
15
14
13 12
11 10
9
8
7
6
5
4
3
2
1
0
RST Match Flag Full Flag Reserved
CAM/RAM Part.
Comp. Mask AR Inc/Dec
Mode
128 CAM/0 RAM = 000
96 CAM/32 RAM = 001
64 CAM/64 RAM = 010
32 CAM/96 RAM = 011
96 RAM/32 CAM = 100
64 RAM/64 CAM = 101
32 RAM/96 CAM = 110
No Change = 111
None = 00
MR1 = 01
MR2 = 10
No Change
= 11
Increment
= 00
Decrement
= 01
Disable
= 10
No Change
= 11
R
E
S
E
T
=
0
Enable
= 00
Disable
= 01
No Change No Change
= 11 = 11
Enable
= 00
Disable
= 01
Must be
Set = 00
Standard Mode
= 00
Enhanced Mode
= 01
Reserved
= 10
No Change
= 11
Note: D15 reads back as 0.
Table 9: Control Register Bit Assignments
Rev. 1a
22
MUSIC [ MUSIC SEMICONDUCTORS ]
