MU9C1965A/L LANCAM MP
OPERATIONAL CHARACTERISTICS Continued
/E
/W
/CM
/EC
DQ31-0
DAT A OU T
Figure 2: Read Cycle
/E
/W
/CM
/EC
DQ31-0
Figure 3: Write Cycle
COM PARAN D W RITE
CYC L E
STATUS READ
CYCL E
ASS OC IAT ED D ATA
REA D C YCL E
/E
/CM
/W
DQ31-0
DA TA
DATA
DATA
/EC
/M F
M AT CH FLAG VA LID
/M A, /M M
/M A A ND /M M FL AGS UPDAT ED
Figure 4: Cycle to Cycle Timing Example
cycle-to-cycle timing with the Match flag valid at the end
of the Comparand Write cycle, assuming /EC is LOW at the
start of this cycle. Data writes and reads to the Comparand,
mask registers or memory occur in one to four 32-bit cycles,
depending on the settings in the Segment Control register.
The Compare operation automatically occurs during Data
writes to the Comparand or mask registers when the
destination segment counter reaches the end count set in
the Segment Control register. If there was a match, the
second cycle reads status or associated data, depending
on the state of /CM. For cascaded devices, /EC needs to be
LOW at the start of the cycle prior to any cycle that requires
a locked daisy chain, such as a Status register or associated
data read after a match. If there is no match in Standard
mode, the output buffers stay Hi-Z, and the daisy chain
must be unlocked by taking /EC HIGH during a NOP or
other non-functioning cycle, as indicated in Table 6a on
page 12. Figure 5 shows how the internal /EC timing holds
the daisy chain locking effect over into the next cycle. In
Enhanced mode, this NOP is not needed before data or
command writes following a non-matching compare, as
indicated by Table 6b on page 12. A single-chip system
does not require daisy-chained match flag operation, hence
/EC could be tied HIGH and the /MA pin or flag in the
Status register used instead of /MF, allowing access to the
device regardless of the match condition.
Rev. 1a
14
MUSIC [ MUSIC SEMICONDUCTORS ]
