MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 13-28. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
M6
M7
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
MII_TX_CLK pulse width high
5
—
25
ns
—
35
65%
MII_TX_CLK
period
M8
MII_TX_CLK pulse width low
35%
65%
MII_TX_CLK
period
Figure 13-71 shows the MII transmit signal timing diagram.
M7
MII_TX_CLK (Input)
M5
M8
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 13-71. MII Transmit Signal Timing Diagram
13.3 MII Async Inputs Signal Timing (MII_CRS,
MII_COL)
Table 13-29 provides information on the MII async inputs signal timing.
Table 13-29. MII Async Inputs Signal Timing
Num
Characteristic
Min
Max
Unit
M9
MII_CRS, MII_COL minimum pulse width
1.5
—
MII_TX_CLK
period
Figure 13-72 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 13-72. MII Async Inputs Timing Diagram
68
MPC860 Family Hardware Specifications
MOTOROLA
MOTOROLA [ MOTOROLA ]
