Bus Signal Timing
Table 9-11 shows the reset timing for the MPC860.
Table 9-11. Reset Timing
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Num
Characteristic
Min
Max
Min
Max
Min
Max
Min
Max
R69 CLKOUT to HRESET high
impedance
—
—
20.00
—
—
20.00
—
—
20.00
—
20.00
ns
ns
ns
R70 CLKOUT to SRESET high
impedance
20.00
20.00
20.00
—
20.00
R71 RSTCONF pulse width
515.15
—
—
—
—
425.00
—
340.00
—
—
—
—
257.58
—
—
—
—
R72
—
—
—
R73 Configuration data to HRESET rising 504.55
edge setup time
425.00
350.00
277.27
ns
ns
ns
ns
ns
ns
ns
R74 Configuration data to RSTCONF
rising edge setup time
350.00
0.00
0.00
—
—
—
350.00
0.00
—
—
350.00
0.00
0.00
—
—
—
350.00
0.00
0.00
—
—
—
R75 Configuration data hold time after
RSTCONF negation
R76 Configuration data hold time after
HRESET negation
—
0.00
—
—
—
R77 HRESET and RSTCONF asserted to
data out drive
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
R78 RSTCONF negated to data out high
impedance
—
—
—
—
—
R79 CLKOUT of last rising edge before
chip three-state HRESET to data out
high impedance
—
—
—
R80 DSDI, DSCK setup
90.91
0.00
—
—
—
75.00
0.00
—
—
—
60.00
0.00
—
—
—
45.45
0.00
—
—
—
ns
ns
ns
R81 DSDI, DSCK hold time
R82 SRESET negated to CLKOUT rising 242.42
edge for DSDI and DSCK sample
200.00
160.00
121.21
Figure 9-31 shows the reset timing for the data bus configuration.
MOTOROLA
MPC860 Family Hardware Specifications
39
MOTOROLA [ MOTOROLA ]
