Bus Signal Timing
Table 9-10. Debug Port Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
P61 DSCK cycle time
3 × T
—
—
—
—
ns
ns
ns
ns
ns
CLOCKOUT
P62 DSCK clock pulse width
P63 DSCK rise and fall times
P64 DSDI input data setup time
P65 DSDI data hold time
1.25 × T
CLOCKOUT
0.00
3.00
—
8.00
5.00
0.00
0.00
—
P66 DSCK low to DSDO data valid
P67 DSCK low to DSDO invalid
15.00
2.00
Figure 9-29 provides the input timing for the debug port clock.
DSCK
D61
D62
D61
D62
D63
D63
Figure 9-29. Debug Port Clock Input Timing
Figure 9-30 provides the timing for the debug port.
DSCK
D64
D65
DSDI
D66
D67
DSDO
Figure 9-30. Debug Port Timings
38
MPC860 Family Hardware Specifications
MOTOROLA
MOTOROLA [ MOTOROLA ]
