Bus Signal Timing
1
PSST = 1. Otherwise add PSST times cycle time.
PSHT = 0. Otherwise add PSHT times cycle time.
These synchronous timings define when the WAITx signals are detected in order to freeze
(or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is
detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC860
PowerQUICC User s Manual.
Figure 9-24 provides the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
P44
A[0:31]
P46
P48
P45
P47
P49
P51
P52
REG
CE1/CE2
PCOE, IORD
ALE
P50
P53
P52
B18
B19
D[0:31]
Figure 9-24. PCMCIA Access Cycles Timing External Bus Read
Figure 9-25 provides the PCMCIA access cycle timing for the external bus write.
MOTOROLA
MPC860 Family Hardware Specifications
35
MOTOROLA [ MOTOROLA ]
