Bus Signal Timing
HRESET
R71
R76
RSTCONF
D[0:31] (IN)
R73
R74
R75
Figure 9-31. Reset Timing—Configuration from Data Bus
Figure 9-32 provides the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77
R78
D[0:31] (OUT)
(Weak)
Figure 9-32. Reset Timing—Data Bus Weak Drive During Configuration
Figure 9-33 provides the reset timing for the debug port configuration.
40
MPC860 Family Hardware Specifications
MOTOROLA