IEEE 1149.1 Electrical Specifications
CLKOUT
SRESET
R70
R81
R82
R80
R80
R81
DSCK, DSDI
Figure 9-33. Reset Timing—Debug Port Configuration
Part X IEEE 1149.1 Electrical Specifications
Table 10-12 provides the JTAG timings for the MPC860 shown in Figure 10-34 through
Figure 10-37.
Table 10-12. JTAG Timing
All Frequencies
Num
Characteristic
Unit
Min
Max
J82 TCK cycle time
100.00
40.00
0.00
5.00
25.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
J83 TCK clock pulse width measured at 1.5 V
J84 TCK rise and fall times
10.00
—
J85 TMS, TDI data setup time
J86 TMS, TDI data hold time
—
J87 TCK low to TDO data valid
27.00
—
J88 TCK low to TDO data invalid
0.00
—
J89 TCK low to TDO high impedance
J90 TRST assert time
20.00
—
100.00
40.00
—
J91 TRST setup time to TCK low
—
J92 TCK falling edge to output valid
J93 TCK falling edge to output valid out of high impedance
J94 TCK falling edge to output high impedance
J95 Boundary scan input valid to TCK rising edge
J96 TCK rising edge to boundary scan input invalid
50.00
50.00
50.00
—
—
—
50.00
50.00
—
MOTOROLA
MPC860 Family Hardware Specifications
41
MOTOROLA [ MOTOROLA ]
