Freescale Semiconductor, Inc.
Appendix: CGM Practical Aspects
Printed Circuit Board Guidelines
In addition to the above general pieces of advice, the following
guidelines should be followed for the CGM pins (but also more generally
for any sensitive analog circuitry):
• Parasitic capacitance on EXTAL is absolutely critical – probably
the most critical layout consideration. The XTAL pin is not as
sensitive. All routing from the EXTAL pin through the resonator
and the blocking cap to the actual connection to VSS must be
considered.
• For minimum capacitance there should ideally be no ground /
power plane around the EXTAL pin and associated routing.
However, practical EMC considerations obviously should be taken
into consideration for each application.
• The clock input circuitry is sensitive to noise so excellent supply
routing and decoupling is mandatory. Connect the ground point of
the oscillator circuit directly to the VSSPLL pin.
• Good isolation of PLL / Oscillator Power supply is critical. Use
1nF+ 100nF and keep tracks as low impedance as possible
• Load capacitors should be low leakage and stable across
temperature – use NPO or C0G types.
• The load capacitors may ‘pull’ the target frequency by a few ppm.
Crystal manufacturer specs show symmetrical values but the
series device capacitance on EXTAL and XTAL are not
symmetrical. It may be possible to adjust this by changing the
values of the load capacitors – start-up conditions should be
evaluated.
• Keep the adjacent Port H / Port E and RESET signals noise free.
Don’t connect these to external signals and / or add series filtering
– a series resistor is probably adequate.
• Any DC-blocking capacitor should be as low ESR as possible – for
the range of crystals we are looking at anything over 1 Ohm is too
much.
• Mount oscillator components on MCU side of board – avoid using
vias in the oscillator circuitry.
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Appendix: CGM Practical Aspects
397
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