Freescale Semiconductor, Inc.
Appendix: 68HC912D60A Flash EEPROM
22.3 Overview
The Flash EEPROM array is arranged in a 16-bit configuration and may
be read as either bytes, aligned words or misaligned words. Access time
is one bus cycle for byte and aligned word access and two bus cycles for
misaligned word operations.
Programming is by aligned word. The Flash EEPROM module supports
bulk erase only.
Each Flash EEPROM module has hardware interlocks which protect
stored data from accidental corruption. An erase- and program-
protected 8-Kbyte block for boot routines is located at $6000–$7FFF or
$E000–$FFFF depending upon the mapped location of the Flash
EEPROM arrays.
22.4 Flash EEPROM Control Block
A 4-byte register block for each module controls the Flash EEPROM
operation. Configuration information is specified and programmed
independently from the contents of the Flash EEPROM array. At reset,
the 4-byte register section starts at address $00F4/$00F8.
22.5 Flash EEPROM Arrays
After reset, the 32K Flash EEPROM array is located from addresses
$8000 to $FFFF and the 28K Flash EEPROM array is from $1000 to
$7FFF. In expanded modes, the Flash EEPROM arrays are turned off.
The Flash EEPROM can be mapped to an alternate address range. See
Operating Modes and Resource Mapping.
Advance Information
400
68HC(9)12D60 — Rev 4.0
Appendix: 68HC912D60A Flash EEPROM
MOTOROLA
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