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XC68HC912D60FU8 参数 Datasheet PDF下载

XC68HC912D60FU8图片预览
型号: XC68HC912D60FU8
PDF下载: 下载PDF文件 查看货源
内容描述: 超前信息 - 冯4.0 [Advance Information - Rev 4.0]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 432 页 / 2948 K
品牌: MOTOROLA [ MOTOROLA ]
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Freescale Semiconductor, Inc.  
Appendix: CGM Practical Aspects  
Printed Circuit Board Guidelines  
21.5 Printed Circuit Board Guidelines  
Printed Circuit Boards (PCBs) are the board of choice for volume  
applications. If designed correctly, a very low noise system can be built  
on a PCB with consequently good EMI/EMC performances. If designed  
incorrectly, PCBs can be extremely noisy and sensitive modules, and  
the CGM could be disrupted. Some common sense rules can be used to  
prevent such problems.  
• Use a ‘star’ style power routing plan as opposed to a ‘daisy chain’.  
Route power and ground from a central location to each chip  
individually, and use the widest trace practical (the more the chip  
draws current, the wider the trace). NEVER place the MCU at the  
end of a long string of serially connected chips.  
• When using PCB layout software, first direct the routing of the  
power supply lines as well as the CGM wires (crystal oscillator and  
PLL). Layout constraints must be then reported on the other  
signals and not on these ‘hot’ nodes. Optimizing the ‘hot’ nodes at  
the end of the routing process usually gives bad results.  
• Avoid notches in power traces. These notches not only add  
resistance (and are not usually accounted for in simulations), but  
they can also add unnecessary transmission line effects.  
• Avoid ground and power loops. This has been one of the most  
violated guidelines of PCB layout. Loops are excellent noise  
transmitters and can be easily avoided. When using multiple layer  
PCBs, the power and ground plane concept works well but only  
when strictly adhered to (do not compromise the ground plane by  
cutting a hole in it and running signals on the ground plane layer).  
Keep the spacing around via holes to a minimum (but not so small  
as to add capacitive effects).  
• Be aware of the three dimensional capacitive effects of multi-  
layered PCBs.  
• Bypass (decouple) the power supplies of all chips as close to the  
chip as possible. Use one decoupling capacitor per power supply  
pair (VDD/VSS, VDDX/VSSX...). Two capacitors with a ratio of  
about 100 sometimes offer better performances over a broader  
68HC(9)12D60 — Rev 4.0  
MOTOROLA  
Advance Information  
Appendix: CGM Practical Aspects  
395  
For More Information On This Product,  
Go to: www.freescale.com  
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