Freescale Semiconductor, Inc.
Pulse Width Modulator
PWM Register Description
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over or
the channel is disabled. Reading this register returns the most recent
value written.
If the duty register is greater than or equal to the value in the period
register, there will be no duty change in state. If the duty register is set
to $FF the output will always be in the state which would normally be the
state opposite the PPOLx value.
Left-Aligned-Output Mode (CENTR = 0):
Duty cycle = [(PWDTYx + 1) / (PWPERx + 1)] × 100%
(PPOLx = 1)
Duty cycle = [(PWPERx−PWDTYx)/(PWPERx+1)]×100% (PPOLx = 0)
Center-Aligned-Output Mode (CENTR = 1):
Duty cycle = [(PWPERx−PWDTYx)/PWPERx]×100%
Duty cycle = [PWDTYx / PWPERx] × 100%
(PPOLx = 0)
(PPOLx = 1)
Bit 7
6
0
0
5
0
0
4
PSWAI
0
3
CENTR
0
2
RDPP
0
1
PUPP
0
Bit 0
0
0
PSBCK
0
RESET:
PWCTL — PWM Control Register
$0054
Read and write anytime.
PSWAI — PWM Halts while in Wait Mode
0 = Allows PWM main clock generator to continue while in wait
mode.
1 = Halt PWM main clock generator when the part is in wait mode.
CENTR — Center-Aligned Output Mode
To avoid irregularities in the PWM output mode, write the CENTR bit
only when PWM channels are disabled.
0 = PWM channels operate in left-aligned output mode
1 = PWM channels operate in center-aligned output mode
68HC(9)12D60 — Rev 4.0
MOTOROLA
Advance Information
Pulse Width Modulator
193
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