Table 3 MC68HC11A8 Register and Control Bit Assignments (Sheet 2 of 2)
(The register block can be remapped to any 4K boundary.)
Bit 7
DDRA7
Bit 7
6
5
4
PEDGE
4
3
2
1
Bit 0
RTR0
Bit 0
SPR0
0
$1026
$1027
$1028
$1029
$102A
$102B
$102C
$102D
$102E
$102F
$1030
$1031
$1032
$1033
$1034
$1035
$1038
$1039
$103A
$103B
$103C
$103D
$103E
$103F
PAEN
PAMOD
0
0
RTR1
PACTL
PACNT
SPCR
6
5
3
CPOL
0
2
1
SPIE
SPIF
Bit 7
SPE
DWOM
MSTR
MODF
4
CPHA
SPR1
WCOL
0
0
2
0
SPSR
6
5
SCP1
0
3
1
SCR1
0
Bit 0
SCR0
0
SPDR
TCLR
R8
0
T8
TCIE
TC
R6/T6
0
SCP0
M
RCKB
WAKE
TE
SCR2
0
BAUD
SCCR1
SCCR2
SCSR
TIE
RIE
RDRF
R5/T5
SCAN
5
ILIE
IDLE
R4/T4
MULT
4
RE
NF
R2/T2
CC
2
RWU
FE
R1/T1
CB
1
SBK
0
TDRE
R7/T7
CCF
Bit 7
OR
R3/T3
CD
3
R0/T0
CA
SCDR
ADCTL
ADR1
6
Bit 0
Bit 0
Bit 0
Bit 0
Bit 7
6
5
4
3
2
1
ADR2
Bit 7
6
5
4
3
2
1
ADR3
Bit 7
6
5
4
3
2
1
ADR4
Reserved
Reserved
OPTION
COPRST
PPROG
HPRIO
INIT
ADPU
Bit 7
CSEL
6
IRQE
5
DLY
4
CME
3
0
CR1
1
CR0
Bit 0
2
ODD
EVEN
SMOD
RAM2
0
0
BYTE
IRV
ROW
PSEL3
REG3
DISR
NOSEC
ERASE
PSEL2
REG2
FCM
EELAT
PSEL1
REG1
FCOP
EEPGM
PSEL0
REG0
TCON
EEON
RBOOT
RAM3
TILOP
0
MDA
RAM1
OCCR
0
RAM0
CBYP
0
TEST1
CONFIG
0
NOCOP ROMON
MOTOROLA
10
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA [ MOTOROLA ]
