Table 4 Interrupt and Reset Vector Assignments
Vector Address
FFC0, C1 – FFD4, D5
FFD6, D7
Interrupt Source
Reserved
CCR Mask
Local Mask
—
—
SCI Serial System
I Bit
• SCI Transmit Complete
• SCI Transmit Data Register Empty
• SCI Idle Line Detect
• SCI Receiver Overrun
• SCI Receive Data Register Full
SPI Serial Transfer Complete
Pulse Accumulator Input Edge
Pulse Accumulator Overflow
Timer Overflow
TCIE
TIE
ILIE
RIE
RIE
FFD8, D9
FFDA, DB
FFDC, DD
FFDE, DF
FFE0, E1
FFE3, E2
FFE4, E5
FFE6, E7
FFE8, E9
FFEA, EB
FFEC, ED
FFEE, EF
FFF0, F1
FFF2, F3
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
SPIE
PAII
PAOVI
TOI
Timer Input Capture 4/Output Compare 5
Timer Output Compare 4
Timer Output Compare 3
Timer Output Compare 2
Timer Output Compare 1
Timer Input Capture 3
Timer Input Capture 2
Timer Input Capture 1
Real-Time Interrupt
I4O5I
OC4I
OC3I
OC2I
OC1I
IC3
IC2I
IC1I
RTII
Parallel I/O Handshake
IRQ
STAI
None
None
None
None
NOCOP
CME
None
FFF4, F5
FFF6, F7
FFF8, F9
FFFA, FB
FFFC, FD
FFFE, FF
XIRQ Pin
X Bit
None
None
None
None
None
Software Interrupt
Illegal Opcode Trap
COP Failure
COP Clock Monitor Fail
RESET
OPTION —System Configuration Options
$1039
Bit 7
ADPU
0
6
CSEL
0
5
IRQE*
0
4
DLY*
1
3
CME
0
2
0
0
1
CR1*
0
Bit 0
CR0*
0
RESET:
*Can be written only once in first 64 cycles out of reset in normal modes, or any time in special modes.
ADPU —A/D Converter Power-up
Refer to 10 Analog-to-Digital Converter.
CSEL —Clock Select
Refer to 10 Analog-to-Digital Converter.
IRQE — IRQ Select Edge-Sensitive Only
0 = Low logic level recognition
1 = Falling edge recognition
MOTOROLA
14
MC68HC11A8
MC68HC11A8TS/D
MOTOROLA [ MOTOROLA ]
