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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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CPU32 interprets multiple vector numbers at the same time, with un-  
predictable consequences.  
Because the EBI manages external interrupt requests, the SIM IARB value is used for  
arbitration between internal and external interrupt requests. The reset value of IARB  
for the SIM is %1111, and the reset IARB value for all other modules is %0000.  
Although arbitration is intended to deal with simultaneous requests of the same prior-  
ity, it always takes place, even when a single source is requesting service. This is im-  
portant for two reasons: the EBI does not transfer the interrupt acknowledge read cycle  
to the external bus unless the SIM wins contention, and failure to contend causes the  
interrupt acknowledge bus cycle to be terminated early, by a bus error.  
When arbitration is complete, the module with the highest arbitration priority must ter-  
minate the bus cycle. Internal modules place an interrupt vector number on the data  
bus and generate appropriate internal cycle termination signals. In the case of an ex-  
ternal interrupt request, after the interrupt acknowledge cycle is transferred to the ex-  
ternal bus, the appropriate external device must decode the mask value and respond  
with a vector number, then generate data and size acknowledge (DSACK) termination  
signals, or it must assert the autovector (AVEC) request signal. If the device does not  
respond in time, the EBI bus monitor asserts the bus error signal BERR, and a spuri-  
ous interrupt exception is taken.  
4
Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-  
sponse to interrupt requests from external devices (refer to 4.8.3 Using Chip-Select  
Signals for Interrupt Acknowledge). Chip-select address match logic functions only  
after the EBI transfers an interrupt acknowledge cycle to the external bus following  
IARB contention. If a module makes an interrupt request of a certain priority, and the  
appropriate chip-select registers are programmed to generate AVEC or DSACK sig-  
nals in response to an interrupt acknowledge cycle for that priority level, chip-select  
logic does not respond to the interrupt acknowledge cycle, and the internal module  
supplies a vector number and generates internal cycle termination signals.  
For periodic timer interrupts, the PIRQ field in the periodic interrupt control register (PI-  
CR) determines PIT priority level. A PIRQ value of %000 means that PIT interrupts are  
inactive. By hardware convention, when the CPU32 receives simultaneous interrupt  
requests of the same level from more than one SIM source (including external devic-  
es), the periodic interrupt timer is given the highest priority, followed by the IRQ pins.  
4.7.4 Interrupt Processing Summary  
A summary of the entire interrupt processing sequence follows. When the sequence  
begins, a valid interrupt service request has been detected and is pending.  
A. The CPU finishes higher priority exception processing or reaches an instruction  
boundary.  
B. The processor state is stacked. The S bit in the status register is set, establish-  
ing supervisor access level, and bits T1 and T0 are cleared, disabling tracing.  
C. The interrupt acknowledge cycle begins:  
1. FC[2:0] are driven to %111 (CPU space) encoding.  
MC68331  
SYSTEM INTEGRATION MODULE  
MOTOROLA  
4-47  
USER’S MANUAL