If an internal source asserts a reset signal, the reset control logic asserts RESET for
a minimum of 512 cycles. If the reset signal is still asserted at the end of 512 cycles,
the control logic continues to assert RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance
state for ten cycles. At the end of this 10-cycle period, the reset input is tested. When
the input is at logic level one, reset exception processing begins. If, however, the reset
input is at logic level zero, the reset control logic drives the pin low for another 512 cy-
cles. At the end of this period, the pin again goes to high-impedance state for ten cy-
cles, then it is tested again. The process repeats until RESET is released.
4.6.7 Power-On Reset
When the SIM clock synthesizer is used to generate system clocks, power-on reset in-
volves special circumstances related to application of system and clock synthesizer
power. Regardless of clock source, voltage must be applied to clock synthesizer pow-
er input pin V
for the MCU to operate. The following discussion assumes that
DDSYN
V
is applied before and during reset, which minimizes crystal start-up time.
DDSYN
When V
is applied at power-on, start-up time is affected by specific crystal pa-
DDSYN
rameters and by oscillator circuit design. V
ing reset. Refer to APPENDIX A ELECTRICAL CHARACTERISTICS for voltage and
timing specifications.
ramp-up time also affects pin state dur-
DD
4
During power-on reset, an internal circuit in the SIM drives the IMB internal (MSTRST)
and external (EXTRST) reset lines. The circuit releases MSTRST as V
ramps up to
DD
the minimum specified value, and SIM pins are initialized as shown in Table 4-19. As
reaches specified minimum value, the clock synthesizer VCO begins operation
V
DD
and clock frequency ramps up to specified limp mode frequency. The external RESET
line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles
elapse line remains asserted until the clock synthesizer PLL locks and 512 CLKOUT
cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the
clock is running and MSTRST is asserted for at least four clock cycles, these modules
reset. V
ramp time and VCO frequency ramp time determine how long the four cy-
DD
cles take. Worst case is approximately 15 milliseconds. During this period, module
port pins may be in an indeterminate state. While input-only pins can be put in a known
state by external pull-up resistors, external logic on input/output or output-only pins
during this time must condition the lines. Active drivers require high-impedance buffers
or isolation resistors to prevent conflict.
Figure 4-16 is a timing diagram of power-up reset. It shows the relationships between
RESET, V , and bus signals.
DD
MC68331
USER’S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA
4-43
MOTOROLA [ MOTOROLA ]
