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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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4.6.9 Reset Status Register  
The reset status register (RSR) contains a bit for each reset source in the MCU. When  
a reset occurs, a bit corresponding to the reset type is set. When multiple causes of  
reset occur at the same time, more than one bit in RSR may be set. The reset status  
register is updated by the reset control logic when the RESET signal is released. Refer  
to APPENDIX D REGISTER SUMMARY.  
4.7 Interrupts  
Interrupt recognition and servicing involve complex interaction between the system in-  
tegration module, the central processing unit, and a device or module requesting in-  
terrupt service. This discussion provides an overview of the entire interrupt process.  
Chip-select logic can also be used to respond to interrupt requests. Refer to 4.8 Chip  
Selects for more information.  
4.7.1 Interrupt Exception Processing  
The CPU32 processes resets as a type of asynchronous exception. An exception is  
an event that preempts normal processing. Each exception has an assigned vector in  
an exception vector table that points to an associated handler routine. The CPU uses  
vector numbers to calculate displacement into the table. During exception processing,  
the CPU fetches the appropriate vector and executes the exception handler routine to  
which the vector points.  
4
Out of reset, the exception vector table is located beginning at address $000000. This  
value can be changed by programming the vector base register (VBR) with a new val-  
ue, and multiple vector tables can be used. Refer to SECTION 5 CENTRAL PRO-  
CESSING UNIT for more information concerning exceptions.  
4.7.2 Interrupt Priority and Recognition  
The CPU32 provides eight levels of interrupt priority. All interrupts with priorities less  
than seven can be masked by the interrupt priority (IP) field in status register.  
There are seven interrupt request signals (IRQ[7:1]). These signals are used internally  
on the IMB, and are corresponding pins for external interrupt service requests. The  
CPU treats all interrupt requests as though they come from internal modules — exter-  
nal interrupt requests are treated as interrupt service requests from the SIM. Each of  
the interrupt request signals corresponds to an interrupt priority level. IRQ1 has the  
lowest priority and IRQ7 the highest.  
Interrupt recognition is determined by interrupt priority level and interrupt priority mask  
value, interrupt recognition is determined by interrupt priority level and interrupt priority  
mask value. The interrupt priority mask consists of three bits in the CPU32 status reg-  
ister. Binary values %000 to %111 provide eight priority masks. Masks prevent an in-  
terrupt request of a priority less than or equal to the mask value from being recognized  
and processed. IRQ7, however, is always recognized, even if the mask value is %111.  
IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted  
until an interrupt acknowledge cycle corresponding to that level is detected.  
MC68331  
SYSTEM INTEGRATION MODULE  
MOTOROLA  
4-45  
USER’S MANUAL