欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
 浏览型号MC68331CPV16的Datasheet PDF文件第84页浏览型号MC68331CPV16的Datasheet PDF文件第85页浏览型号MC68331CPV16的Datasheet PDF文件第86页浏览型号MC68331CPV16的Datasheet PDF文件第87页浏览型号MC68331CPV16的Datasheet PDF文件第89页浏览型号MC68331CPV16的Datasheet PDF文件第90页浏览型号MC68331CPV16的Datasheet PDF文件第91页浏览型号MC68331CPV16的Datasheet PDF文件第92页  
IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected  
unless a falling edge transition is detected on the IRQ7 line. This prevents redundant  
servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is  
asserted as well as each time the priority mask changes from %111 to a lower number  
while IRQ7 is asserted.  
Interrupt requests are sampled on consecutive falling edges of the system clock. In-  
terrupt request input circuitry has hysteresis: to be valid, a request signal must be as-  
serted for at least two consecutive clock periods. Valid requests do not cause  
immediate exception processing, but are left pending. Pending requests are pro-  
cessed at instruction boundaries or when exception processing of higher-priority ex-  
ceptions is complete.  
The CPU32 does not latch the priority of a pending interrupt request. If an interrupt  
source of higher priority makes a service request while a lower priority request is pend-  
ing, the higher priority request is serviced. If an interrupt request with a priority equal  
to or lower than the current IP mask value is made, the CPU32 does not recognize the  
occurrence of the request. If simultaneous interrupt requests of different priorities are  
made, and both have a priority greater than the mask value, the CPU32 recognizes  
the higher-level request.  
4
4.7.3 Interrupt Acknowledge and Arbitration  
When the CPU32 detects one or more interrupt requests of a priority higher than the  
interrupt priority mask value, it places the interrupt request level on the address bus  
and initiates a CPU space read cycle. The request level serves two purposes: it is de-  
coded by modules or external devices that have requested interrupt service, to deter-  
mine whether the current interrupt acknowledge cycle pertains to them, and it is  
latched into the interrupt priority mask field in the CPU32 status register, to preclude  
further interrupts of lower priority during interrupt service.  
Modules or external devices that have requested interrupt service must decode the in-  
terrupt priority mask value placed on the address bus during the interrupt acknowledge  
cycle and respond if the priority of the service request corresponds to the mask value.  
However, before modules or external devices respond, interrupt arbitration takes  
place.  
Arbitration is performed by means of serial contention between values stored in indi-  
vidual module interrupt arbitration (IARB) fields. Each module that can make an inter-  
rupt service request, including the SIM, has an IARB field in its configuration register.  
IARB fields can be assigned values from %0000 to %1111. In order to implement an  
arbitration scheme, each module that can initiate an interrupt service request must be  
assigned a unique, non-zero IARB field value during system initialization. Arbitration  
priorities range from %0001 (lowest) to %1111 (highest) — if the CPU recognizes an  
interrupt service request from a source that has an IARB field value of %0000, a spu-  
rious interrupt exception is processed.  
WARNING  
Do not assign the same arbitration priority to more than one module.  
When two or more IARB fields have the same nonzero value, the  
MOTOROLA  
4-46  
SYSTEM INTEGRATION MODULE  
MC68331  
USER’S MANUAL