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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]  
= %1111, which indicates that the cycle is an interrupt acknowledge CPU  
space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of  
the interrupt request being acknowledged; and ADDR0 = %1.  
3. The request level is latched from the address bus into the interrupt priority  
mask field in the status or condition code register.  
D. Modules that have requested interrupt service decode the priority value in AD-  
DR[3:1]. If request priority is the same as acknowledged priority, arbitration by  
IARB contention takes place.  
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-  
lowing ways:  
1. When there is no contention (IARB = %0000), the spurious interrupt moni-  
tor asserts BERR, and the CPU generates the spurious interrupt vector  
number.  
2. The dominant interrupt source supplies a vector number and DSACK sig-  
nals appropriate to the access. The CPU acquires the vector number.  
3. The AVEC signal is asserted (the signal can be asserted by the dominant  
interrupt source or the pin can be tied low), and the CPU generates an au-  
tovector number corresponding to interrupt priority.  
4
4. The bus monitor asserts BERR and the CPU32 generates the spurious in-  
terrupt vector number.  
F. The vector number is converted to a vector address.  
G. The content of the vector address is loaded into the PC, and the processor  
transfers control to the exception handler routine.  
4.7.5 Interrupt Acknowledge Bus Cycles  
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during  
exception processing. For further information about the types of interrupt acknowledge  
bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL  
CHARACTERISTICS and the SIM Reference Manual (SIMRM/AD).  
4.8 Chip Selects  
Typical microcontrollers require additional hardware to provide external select and ad-  
dress decode signals. The MCU includes 12 programmable chip-select circuits that  
can provide 2- to 20-clock-cycle access to external memory and peripherals. Address  
block sizes of two Kbytes to one Mbyte can be selected. Figure 4-17 is a diagram of  
a basic system that uses chip selects.  
MOTOROLA  
4-48  
SYSTEM INTEGRATION MODULE  
MC68331  
USER’S MANUAL