transfer size. The chip-select option must not be written until a base address has been
written to a proper base address register. CSBOOT is automatically asserted out of
reset. Alternate functions for chip-select pins are enabled if appropriate data bus pins
are held low at the release of the reset signal (refer to 4.6.3.1 Data Bus Mode Selec-
tion for more information). Figure 4-18 is a functional diagram of a single chip-select
circuit.
INTERNAL
BASE ADDRESS REGISTER
SIGNALS
ADDRESS
ADDRESS COMPARATOR
OPTION COMPARE
TIMING
AND
CONTROL
PIN
BUS CONTROL
OPTION REGISTER
4
PIN
ASSIGNMENT
REGISTER
PIN
DATA
REGISTER
AVEC
GENERATOR
DSACK
GENERATOR
AVEC
DSACK
CHIP SEL BLOCK
Figure 4-18 Chip-Select Circuit Block Diagram
4.8.1 Chip-Select Registers
Each chip-select pin can have one or more functions. Ship-select pin assignment reg-
isters (CSPAR[0:1]) determine functions of the pins. Pin assignment registers also de-
termine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC)
latches data for chip-select pins that are used for discrete output.
Blocks of addresses are assigned to each chip-select function. Block sizes of two
Kbytes to one Mbyte can be selected by writing values to the appropriate base address
register (CSBAR[0:10], CSBARBT). Address blocks for separate chip-select functions
can overlap.
Chip select option registers (CSOR[0:10], CSORBT) determine timing of and condi-
tions for assertion of chip-select signals. Eight parameters, including operating mode,
access size, synchronization, and wait state insertion can be specified.
Initialization software usually resides in a peripheral memory device controlled by the
chip-select circuits. A set of special chip-select functions and registers (CSORBT, CS-
BARBT) is provided to support bootstrap operation.
Comprehensive address maps and register diagrams are provided in APPENDIX D
REGISTER SUMMARY.
MOTOROLA
4-50
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
