Table 4-18 SIM Pin Reset States
State While
RESET
Asserted
1
Pin State After RESET Released
Mnemonic
Pin
Function
CS10
Pin State
Pin
Function
ADDR23
Pin State
CS10/ADDR23
CS[9:6]/ADDR[22:19]/PC[6:3]
ADDR[18:0]
AS/PE5
1
1
Unknown
1
CS[9:6]
ADDR[18:0]
AS
ADDR[22:19] Unknown
High-Z Output
High-Z Output
Disabled
Disabled
1
Unknown
Output
Input
Input
1
ADDR[18:0]
PE5
Unknown
Input
AVEC/PE2
BERR
AVEC
PE2
Input
BERR
CSM
BERR
BG
Input
CSM/BG
1
CSE/BGACK
CS0/BR
1
CSE
1
BGACK
BR
Input
1
CS0
1
Input
CLKOUT
Output
1
CLKOUT
CSBOOT
DATA[15:0]
DS
Output
0
CLKOUT
CSBOOT
DATA[15:0]
PE4
Output
0
CSBOOT
DATA[15:0]
DS/PE4
Mode Select
Disabled
Disabled
Disabled
1
Input
Output
Input
Input
1
Input
Input
DSACK0/PE0
DSACK1/PE1
CS5/FC2/PC2
FC1/PC1
DSACK0
DSACK1
CS5
PE0
Input
PE1
Input
4
FC2
Unknown
Unknown
Unknown
Input
1
FC1
1
FC1
CS3/FC0/PC0
HALT
1
CS3
1
FC0
Disabled
Disabled
Mode Select
Disabled
Asserted
Disabled
Disabled
Mode Select
HALT
Input
Input
Input
Output
Input
Output
Unknown
Input
HALT
PF[7:1]
PF0
IRQ[7:1]/PF[7:1]
MODCLK/PF0
R/W
IRQ[7:1]
MODCLK
R/W
Input
Input
R/W
Output
Input
RESET
RESET
RMC
RESET
PE3
RMC
Input
SIZ[1:0]/PE[7:6]
TSC
SIZ[1:0]
TSC
PE[7:6]
TSC
Input
Input
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules
As a rule, module pins that are assigned to general-purpose I/O ports go to active high-
impedance state following reset. Other pin states are determined by individual module
control register settings. Refer to sections concerning modules for details. However,
during power-up reset, module port pins may be in an indeterminate state for a short
period. Refer to 4.6.7 Power-On Reset for more information.
4.6.6 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven, to guarantee this length of reset to the entire system.
MOTOROLA
4-42
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
