4.6.3.2 Clock Mode Selection
The state of the clock mode (MODCLK) pin during reset determines what clock source
the MCU uses. When MODCLK is held high during reset, the clock signal is generated
from a reference frequency. When MODCLK is held low during reset, the clock syn-
thesizer is disabled, and an external system clock signal must be applied. Refer to 4.3
System Clock for more information.
NOTE
The MODCLK pin can also be used as parallel I/O pin PF0. To pre-
vent inadvertent clock mode selection by logic connected to port F,
use an active device to drive MODCLK during reset.
4.6.3.3 Breakpoint Mode Selection
The MCU uses internal and external breakpoint (BKPT) signals. During reset excep-
tion processing, at the release of the RESET signal, the CPU32 samples these signals
to determine how to handle breakpoints.
If either BKPT signal is at logic level zero when sampled, an internal BDM flag is set,
and the CPU32 enters background debugging mode whenever either BKPT input is
subsequently asserted.
4
If both BKPT inputs are at logic level one when sampled, breakpoint exception pro-
cessing begins whenever either BKPT signal is subsequently asserted.
Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information on back-
ground debugging mode and exceptions. Refer to 4.5.4 CPU Space Cycles for infor-
mation concerning breakpoint acknowledge bus cycles.
4.6.4 MCU Module Pin Function During Reset
Usually, module pins default to port functions, and input/output ports are set to input
state. This is accomplished by disabling pin functions in the appropriate control regis-
ters, and by clearing the appropriate port data direction registers. Refer to individual
module sections in this manual for more information. Table 4-17 is a summary of mod-
ule pin function out of reset. Refer to APPENDIX D REGISTER SUMMARY for register
function and reset state.
MOTOROLA
4-40
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
MOTOROLA [ MOTOROLA ]
