Table 5-1 Instruction Set Summary (Continued)
Instruction
NEG
Syntax
<ea>
<ea>
none
Operand Size
8, 16, 32
8, 16, 32
none
Operation
0 – Destination
Destination
Destination
PC
NEGX
NOP
0 – Destination – X
PC + 2
NOT
<ea>
8, 16, 32
Destination
Destination
Destination
OR
<ea>, Dn
Dn, <ea>
8, 16, 32
8, 16, 32
Source; Destination
ORI
#<data>, <ea>
#<data>, CCR
#<data>, SR
<ea>
8, 16, 32
16
Data; Destination
Destination
ORI to CCR
Source; CCR
Source; SR
SR
SR
1
16
ORI to SR
PEA
32
SP – 4
SP; <ea>
SP
1
none
none
Assert RESET line
RESET
ROL
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROR
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ROXL
ROXR
RTD
Dn, Dn
#<data>,
Dn<ea>
8, 16, 32
8, 16, 32
16
5
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
#<d>
none
16
(SP)
PC; SP + 4 + d
SP
SP; (SP)
SP;
1
RTE
none
(SP)
SR; SP + 2
SP + 4
restore stack according to format
PC;
PC;
RTR
none
none
none
(SP)
CCR; SP + 2
SP + 4
SP; (SP)
SP
RTS
none
88
(SP)
PC; SP + 4
SP
SBCD
Dn, Dn
– (An), – (An)
Destination – Source – X
Destination
10 10
Scc
<ea>
8
If condition true, then destination bits are set to 1;
else, destination bits are cleared to 0
1
#<data>
16
Data
SR; STOP
STOP
SUB
<ea>, Dn
Dn, <ea>
8, 16, 32
Destination – Source
Destination
SUBA
SUBI
<ea>, An
16, 32
Destination – Source
Destination – Data
Destination
Destination
Destination
Destination
#<data>, <ea>
#<data>, <ea>
8, 16, 32
8, 16, 32
SUBQ
SUBX
Destination – Data
Dn, Dn
– (An), – (An)
8, 16, 32
8, 16, 32
Destination – Source – X
SWAP
Dn
16
TBLS/TBLU
<ea>, Dn
Dym : Dyn, Dn
8, 16, 32
Dyn – Dym
(Temp * Dn [7 : 0])
Temp
Temp
(Dym * 256) + Temp
Dn
TBLSN/TBLUN
TRAP
<ea>, Dn
Dym : Dyn, Dn
8, 16, 32
none
Dyn – Dym
(Temp * Dn [7 : 0]) / 256
Dym + Temp
Temp
Temp
Dn
#<data>
SSP – 2
SSP – 4
SSP; format/vector offset
SSP; PC (SSP); SR
vector address PC
(SSP);
(SSP);
MC68331
USER’S MANUAL
CENTRAL PROCESSING UNIT
MOTOROLA
5-13
MOTOROLA [ MOTOROLA ]
