Table 5-1 Instruction Set Summary
Instruction
Syntax
Operand Size
Operation
ABCD
Dn, Dn–
(An), – (An)
8
8
Source + Destination + X
Destination
Destination
10 10
ADD
Dn, <ea>
<ea>, Dn
8, 16, 32
8, 16, 32
Source + Destination
ADDA
ADDI
<ea>, An
16, 32
Source + Destination
Immediate data + Destination
Immediate data + Destination
Source + Destination + X
Destination
#<data>, <ea>
#<data>, <ea>
8, 16, 32
8, 16, 32
Destination
ADDQ
ADDX
Destination
Destination
Dn, Dn–
(An), – (An)
8, 16, 32
8, 16, 32
AND
<ea>, Dn
Dn, <ea>
8, 16, 32
8, 16, 32
Source · Destination
Destination
ANDI
#<data>, <ea>
#<data>, CCR
#<data>, SR
8, 16, 32
Data · Destination
Source · CCR
Source · SR
Destination
CCR
ANDI to CCR
8
1
16
SR
ANDI to SR
ASL
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
ASR
Dn, Dn
#<data>, Dn
<ea>
8, 16, 32
8, 16, 32
16
5
Bcc
<label>
8, 16, 32
If condition true, then PC + d
PC
Z;
BCHG
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
(<bit number> of destination
bit of destination
Z
BCLR
BGND
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
(<bit number> of destination
0
bit of destination
If background mode enabled, then enter
background mode, else format/vector offset – (SSP);
PC – (SSP); SR – (SSP); (vector) PC
none
none
BKPT
#<data>
none
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal
instruction.
BRA
<label>
8, 16, 32
PC + d
(<bit number> of destination
bit of destination
SP; PC (SP); PC + d
(<bit number> of destination
PC
BSET
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
Z;
1
BSR
<label>
8, 16, 32
SP – 4
PC
BTST
Dn, <ea>
#<data>, <ea>
8, 32
8, 32
Z
CHK
<ea>, Dn
<ea>, Rn
16, 32
If Dn < 0 or Dn < (ea), then CHK exception
CHK2
8, 16, 32
If Rn < lower bound or Rn > upper bound, then
CHK exception
CLR
CMP
<ea>
8, 16, 32
8, 16, 32
16, 32
0
Destination
<ea>, Dn
(Destination – Source), CCR shows results
(Destination – Source), CCR shows results
(Destination – Data), CCR shows results
(Destination – Source), CCR shows results
Lower bound Rn Upper bound, CCR shows result
CMPA
CMPI
CMPM
CMP2
DBcc
<ea>, An
#<data>, <ea>
(An) +, (An) +
<ea>, Rn
8, 16, 32
8, 16, 32
8, 16, 32
16
Dn, <label>
If condition false, then Dn – 1
if Dn ≠ (– 1), then PC + d
PC;
PC
DIVS/DIVU
<ea>, Dn
32/16
16: 16
Destination / Source
Destination
(signed or unsigned)
MC68331
USER’S MANUAL
CENTRAL PROCESSING UNIT
MOTOROLA
5-11
MOTOROLA [ MOTOROLA ]
