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MC68331CPV16 参数 Datasheet PDF下载

MC68331CPV16图片预览
型号: MC68331CPV16
PDF下载: 下载PDF文件 查看货源
内容描述: 用户手册 [User’s Manual]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 254 页 / 1319 K
品牌: MOTOROLA [ MOTOROLA ]
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5.4 Virtual Memory  
The full addressing range of the CPU32 on the MC68331 is 16 Mbytes in each of eight  
address spaces. Even though most systems implement a smaller physical memory,  
the system can be made to appear to have a full 16 Mbytes of memory available to  
each user program by using virtual memory techniques.  
A system that supports virtual memory has a limited amount of high-speed physical  
memory that can be accessed directly by the processor and maintains an image of a  
much larger virtual memory on a secondary storage device. When the processor at-  
tempts to access a location in the virtual memory map that is not resident in physical  
memory, a page fault occurs. The access to that location is temporarily suspended  
while the necessary data is fetched from secondary storage and placed in physical  
memory. The suspended access is then restarted or continued.  
The CPU32 uses instruction restart, which requires that only a small portion of the in-  
ternal machine state be saved. After correcting the fault, the machine state is restored,  
and the instruction is fetched and started again. This process is completely transpar-  
ent to the application program.  
5.5 Addressing Modes  
5
Addressing in the CPU32 is register-oriented. Most instructions allow the results of the  
specified operation to be placed either in a register or directly in memory. There is no  
need for extra instructions to store register contents in memory.  
There are seven basic addressing modes:  
• Register Direct  
• Register Indirect  
• Register Indirect with Index  
• Program Counter Indirect with Displacement  
• Program Counter Indirect with Index  
• Absolute  
• Immediate  
The register indirect addressing modes include postincrement, predecrement, and off-  
set capability. The program counter indirect mode also has index and offset capabili-  
ties. In addition to these addressing modes, many instructions implicitly specify the  
use of the status register, stack pointer, and/or program counter.  
5.6 Processing States  
The processor is always in one of four processing states: normal, exception, halted, or  
background. The normal processing state is associated with instruction execution; the  
bus is used to fetch instructions and operands and to store results.  
The exception processing state is associated with interrupts, trap instructions, tracing,  
and other exception conditions. The exception may be internally generated explicitly  
by an instruction or by an unusual condition arising during the execution of an instruc-  
tion. Exception processing can be forced externally by an interrupt, a bus error, or a  
reset.  
MC68331  
CENTRAL PROCESSING UNIT  
MOTOROLA  
5-9  
USER’S MANUAL