OUTPUT PINS
PD
SW1, SW2
Band Switch Outputs (PDIP – Pins 13, 14;
SOG – Pins 14, 15)
out
Phase Detector A Output (PDIP, SOG – Pin 6)
SW1 and SW2 provide latched open–drain outputs corre-
sponding to data bits numbers one and two. These outputs
can be tied through external resistors to voltages as high as
Three–state output of phase detector for use as loop error
signal. Double–ended outputs are also available for this pur-
pose (see φ and φ ).
V
R
15 V, independent of the V
supply voltage. These are
DD
Frequency f > f or f Leading: Negative Pulses
V
R
V
typically used for band switch functions. A logic 1 causes the
output to assume a high–impedance state, while a logic 0
causes the output to be low.
Frequency f < f or f Lagging: Positive Pulses
V
R
V
Frequency f = f and Phase Coincidence: High–Imped-
V
R
ance State
φ , φ
R
V
REF
out
Phase Detector B Outputs (PDIP, SOG – Pins 4, 3)
Buffered Reference Oscillator Output (PDIP, SOG –
Pin 15)
These phase detector outputs can be combined externally
for a loop–error signal. A single–ended output is also avail-
Buffered output of on–chip reference oscillator or exter-
nally provided reference–input signal.
able for this purpose (see PD
).
out
If frequency f is greater than f or if the phase of f is
V
R
V
leading, then error information is provided by φ pulsing low.
V
φ
R
remains essentially high.
POWER SUPPLY
If the frequency f is less than f or if the phase of f is
V
R
V
lagging, then error information is provided by φ pulsing low.
R
V
DD
φ
V
remains essentially high.
Positive Power Supply (PDIP, SOG – Pin 5)
If the frequency of f = f and both are in phase, then both
V
R
φ
V
and φ remain high except for a small minimum time
The positive power supply potential. This pin may range
R
period when both pulse low in phase.
from + 3 to + 9 V with respect to V
.
SS
LD
V
SS
Lock Detector Output (PDIP – Pin 8, SOG – Pin 9)
Negative Power Supply (PDIP, SOG – Pin 7)
Essentially a high level when loop is locked (f , f of same
R V
phase and frequency). LD pulses low when loop is out of
lock.
The most negative supply potential. This pin is usually
ground.
TYPICAL APPLICATIONS
4.0 MHz
UHF/VHF
TUNER OR
CATV
φ
FRONT END
–
+
R
f
in
MC12073/74
PRESCALER
MC145155–2
φ
V
1/2 MC1458*
DATA
CLK
ENB
CMOS
MPU/MCU
3
MC14489
KEYBOARD
LED DISPLAY
* The φ and φ outputs are fed to an external combiner/loop filter. See the Phase–Locked Loop — Low–Pass Filter Design page
R
V
foradditionalinformation.Theφ andφ outputsswingrail–to–rail. Therefore, theusershouldbecarefulnottoexceedthecommon
R
V
mode input range of the op amp used in the combiner/loop filter.
Figure 1. Microprocessor–Controlled TV/CATV Tuning System with Serial Interface
MOTOROLA
MC145151–2 through MC145158–2
11
MOTOROLA [ MOTOROLA ]
