MC145156–2 BLOCK DIAGRAM
RA2
RA1
RA0
12 x 8 ROM REFERENCE DECODER
12
LOCK
DETECT
12–BIT
÷
R COUNTER
OSC
in
LD
PD
OSC
REF
out
f
PHASE
DETECTOR
A
CONTROL LOGIC
R
out
out
f
V
MC
PHASE
DETECTOR
B
7–BIT
÷
A COUNTER
10–BIT
÷
N COUNTER
10
f
φ
in
V
φ
R
7
V
SW2
SW1
DD
ENB
LATCH
÷
A COUNTER LATCH
7
÷
N COUNTER LATCH
10
DATA
CLK
2–BIT SHIFT
REGISTER
7–BIT SHIFT REGISTER
10–BIT SHIFT REGISTER
PIN DESCRIPTIONS
÷
A COUNTER BITS
÷
N COUNTER BITS
INPUT PINS
f
in
Frequency Input (Pin 10)
Input to the positive edge triggered ÷ N and ÷ A counters.
LAST DATA BIT IN (BIT NO. 19)
FIRST DATA BIT IN (BIT NO. 1)
f
is typically derived from a dual–modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels), dc coupling may be used.
in
ENB
Latch Enable Input (Pin 13)
RA0, RA1, RA2
When high (1), ENB transfers the contents of the shift reg-
ister into the latches, and to the programmable counter in-
puts, and the switch outputs SW1 and SW2. When low (0),
ENB inhibits the above action and thus allows changes to be
made in the shift register data without affecting the counter
programming and switch outputs. An on–chip pull–up esta-
blishes a continuously high level for ENB when no external
signal is applied. ENB is normally low and is pulsed high to
transfer data to the latches.
Reference Address Inputs (Pins 20, 1, 2)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below:
Total
Divide
Value
Reference Address Code
RA2
RA1
RA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 19, 18)
128
256
640
1000
1024
2048
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSC to ground and OSC
to ground.
in
out
OSC may also serve as the input for an externally–gener-
in
ated reference signal. This signal is typically ac coupled to
CLK, DATA
OSC , but for larger amplitude signals (standard CMOS
in
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
logic levels) dc coupling may also be used. In the external
Each low–to–high transition clocks one bit into the on–chip
19–bit shift register. The data input provides programming in-
formation for the 10–bit ÷ N counter, the 7–bit ÷ A counter,
and the two switch signals SW1 and SW2. The entry format
is as follows:
reference mode, no connection is required to OSC
.
out
TEST
Factory Test Input (Pin 16)
Used in manufacturing. Must be left open or tied to V
SS
.
MC145151–2 through MC145158–2
14
MOTOROLA
MOTOROLA [ MOTOROLA ]
