MT90810
Preliminary Information
into the device due to a DMA write request of a given
channel, is not actually written to that channel but to
the next channel enabled for DMA on the same
stream.
PLL Diagnostic
Diagnostic for the PLL is available via a diagnostic
register. The register contains bits which should
never be set under normal operating conditions. Two
bits in the register SEL_XIN or VCO_BYP may be
set if the user wishes to bypass the internal analog
PLL or VCO, respectively. The bits are defined in
Table 17 - “Diagnostic (DIAG_REG) Register”.
If a DMA read or write request is not completely
served by the time the next request needs to be
asserted, a DMA overrun error occurs. This causes
the corresponding overrun bit in the MCS register, as
well as, the ERR bit to be set. DMA access can be
throttled by disabling DMA for several timeslots in
between channels that have DMA enabled.
Bit
Name
Description (This register is cleared upon reset)
7
PLL_UNLCK
The bit will be asserted if the on-chip PLL goes out of lock. The ERR pin of the FMIC
will also be asserted high. The PLL_UNLCK bit will remain asserted until a zero is
written to it.
6
5
DMAW_OV
DMAR_OV
When asserted, the bits indicate that a DMA overrun condition occurred on the DMA
Read/Write channel, respectively. The ERR pin of the FMIC will also be asserted. The
DMAR/W_OV bits will remain asserted until zeros are written to them.
4
CLK_ERR
The bit monitors activity on the C4b pin of the MVIP bus and is asserted if there has
been no activity on the C4b pin for 4µs. The ERR pin of the FMIC will also be asserted
high. The CLK_ERR bit will remain asserted until a zero is written to it
3
2
1
MVIP_MST
DMA_EN
FMIC_EN
When set, enables the FMIC to drive the MVIP clock signals and consequently to
become master of the MVIP bus. When cleared, FMIC becomes slave of MVIP bus.
The bit should be set to enable DMA operations only after the DMA control registers
have been initialized
When cleared, all MVIP signals are high impedance and LD0&2 are set to logic 1,
LD1&3 are set to logic 0. The bit should be set to enable the FMIC to drive data onto the
streams only after the chip has been initialized
0
RESET
When set, clears all registers in the FMIC control space but does NOT clear connection
and data memory. The bit must be cleared for normal operation
Table 3 - Master Control/Status Register [00]
Bit
Bit Function
7:0
Bits 0 to 7 of the Indirect Address
Table 4 -Low Address Register [01]
Bits
Bit Function
7:6
5:4
Auto increment/decrement mode
[00] Normal Mode - indirect address not auto incremented
[01] Auto increment indirect address after indirect read of IDR
[10] Auto increment indirect address after indirect write of IDR
[11] Auto increment indirect address after indirect read or write of IDR
Selects the memory space:
[00] FMIC Control Registers
[01] Data Memory
[10] Connection Memory Low Byte
[11] Connection Memory High Byte
3:1
0
Reserved
Bit 8 of the Indirect Address
Table 5 - Address Mode Register [10]
2-156
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